On 16.02.2023 10:43, Bartosz Golaszewski wrote:
> On Wed, Feb 15, 2023 at 4:40 PM Bartosz Golaszewski <brgl@xxxxxxxx> wrote:
>>
>> From: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx>
>>
>> Add the serial port connected to the GNSS on sa8775p-ride.
>>
>> Signed-off-by: Bartosz Golaszewski <bartosz.golaszewski@xxxxxxxxxx>
>> ---
>> arch/arm64/boot/dts/qcom/sa8775p-ride.dts | 34 +++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/sa8775p.dtsi | 15 ++++++++++
>> 2 files changed, 49 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
>> index d01ca3a9ee37..47cf26ea49e8 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p-ride.dts
>> @@ -13,6 +13,7 @@ / {
>>
>> aliases {
>> serial0 = &uart10;
>> + serial1 = &uart12;
>> i2c18 = &i2c18;
>> spi16 = &spi16;
>> };
>> @@ -66,6 +67,30 @@ qup_i2c18_default: qup-i2c18-state {
>> drive-strength = <2>;
>> bias-pull-up;
>> };
>> +
>> + qup_uart12_cts: qup-uart12-cts-state {
>> + pins = "gpio52";
>> + function = "qup1_se5";
>> + bias-disable;
>> + };
>> +
>> + qup_uart12_rts: qup_uart12_rts-state {
>> + pins = "gpio53";
>> + function = "qup1_se5";
>> + bias-pull-down;
>> + };
>> +
>> + qup_uart12_tx: qup_uart12_tx-state {
>> + pins = "gpio54";
>> + function = "qup1_se5";
>> + bias-pull-up;
>> + };
>> +
>> + qup_uart12_rx: qup_uart12_rx-state {
>> + pins = "gpio55";
>> + function = "qup1_se5";
>> + bias-pull-down;
>> + };
>> };
>>
>> &uart10 {
>> @@ -75,6 +100,15 @@ &uart10 {
>> status = "okay";
>> };
>>
>> +&uart12 {
>> + pinctrl-0 = <&qup_uart12_cts>,
>> + <&qup_uart12_rts>,
>> + <&qup_uart12_tx>,
>> + <&qup_uart12_rx>;
>> + pinctrl-names = "default";
>> + status = "okay";
>> +};
>> +
>> &xo_board_clk {
>> clock-frequency = <38400000>;
>> };
>> diff --git a/arch/arm64/boot/dts/qcom/sa8775p.dtsi b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> index 1abb545ff4f4..8b8931ea739d 100644
>> --- a/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/sa8775p.dtsi
>> @@ -489,6 +489,21 @@ &clk_virt SLAVE_QUP_CORE_1 0>,
>> operating-points-v2 = <&qup_opp_table_100mhz>;
>> status = "disabled";
>> };
>> +
>> + uart12: serial@a94000 {
>> + compatible = "qcom,geni-uart";
>> + reg = <0x0 0xa94000 0x0 0x4000>;
>> + interrupts = <GIC_SPI 585 IRQ_TYPE_LEVEL_HIGH>;
>
> Please disregard this series, I've just noticed I didn't stage the
> change to the interrupt number here which is wrong. And I need to fix
> the underscores in node names too.
Generally it would be "nicer" if you split adding the nodes
in the SoC and device DTs as well, since you're already resending..
Konrad
>
> Bart
>
>> + clocks = <&gcc GCC_QUPV3_WRAP1_S5_CLK>;
>> + clock-names = "se";
>> + interconnects = <&clk_virt MASTER_QUP_CORE_1 0
>> + &clk_virt SLAVE_QUP_CORE_1 0>,
>> + <&gem_noc MASTER_APPSS_PROC 0
>> + &config_noc SLAVE_QUP_1 0>;
>> + interconnect-names = "qup-core", "qup-config";
>> + power-domains = <&rpmhpd SA8775P_CX>;
>> + status = "disabled";
>> + };
>> };
>>
>> qupv3_id_2: geniqup@8c0000 {
>> --
>> 2.37.2
>>
