On 15.02.2023 08:03, Manivannan Sadhasivam wrote:
> Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
> to the CPU cores. But this relationship is not represented in DTS so far.
>
> So let's make cpufreq node as the clock provider and CPU nodes as the
> consumers. The clock index for each CPU node is based on the frequency
> domain index.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> arch/arm64/boot/dts/qcom/sc8280xp.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> index 813fb168801f..a1eb9e333699 100644
> --- a/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc8280xp.dtsi
> @@ -45,6 +45,7 @@ CPU0: cpu@0 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0x0 0x0>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> capacity-dmips-mhz = <602>;
> next-level-cache = <&L2_0>;
> @@ -69,6 +70,7 @@ CPU1: cpu@100 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0x0 0x100>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> capacity-dmips-mhz = <602>;
> next-level-cache = <&L2_100>;
> @@ -89,6 +91,7 @@ CPU2: cpu@200 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0x0 0x200>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> capacity-dmips-mhz = <602>;
> next-level-cache = <&L2_200>;
> @@ -109,6 +112,7 @@ CPU3: cpu@300 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0x0 0x300>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> capacity-dmips-mhz = <602>;
> next-level-cache = <&L2_300>;
> @@ -129,6 +133,7 @@ CPU4: cpu@400 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0x0 0x400>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> next-level-cache = <&L2_400>;
> @@ -149,6 +154,7 @@ CPU5: cpu@500 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0x0 0x500>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> next-level-cache = <&L2_500>;
> @@ -169,6 +175,7 @@ CPU6: cpu@600 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0x0 0x600>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> next-level-cache = <&L2_600>;
> @@ -189,6 +196,7 @@ CPU7: cpu@700 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0x0 0x700>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> capacity-dmips-mhz = <1024>;
> next-level-cache = <&L2_700>;
> @@ -3875,6 +3883,7 @@ cpufreq_hw: cpufreq@18591000 {
> clock-names = "xo", "alternate";
>
> #freq-domain-cells = <1>;
> + #clock-cells = <1>;
> };
>
> remoteproc_nsp0: remoteproc@1b300000 {
