On 15.02.2023 08:03, Manivannan Sadhasivam wrote:
> Qualcomm platforms making use of CPUFreq HW Engine (EPSS/OSM) supply clocks
> to the CPU cores. But this relationship is not represented in DTS so far.
>
> So let's make cpufreq node as the clock provider and CPU nodes as the
> consumers. The clock index for each CPU node is based on the frequency
> domain index.
>
> Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 9910006c32aa..21b4f668889d 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -68,6 +68,7 @@ CPU0: cpu@0 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0 0>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_0>;
> power-domains = <&CPU_PD0>;
> @@ -91,6 +92,7 @@ CPU1: cpu@100 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0 0x100>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_100>;
> power-domains = <&CPU_PD1>;
> @@ -110,6 +112,7 @@ CPU2: cpu@200 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0 0x200>;
> + clocks = <&cpufreq_hw 0>;
> enable-method = "psci";
> next-level-cache = <&L2_200>;
> power-domains = <&CPU_PD2>;
> @@ -129,6 +132,7 @@ CPU3: cpu@300 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0 0x300>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> next-level-cache = <&L2_300>;
> power-domains = <&CPU_PD3>;
> @@ -148,6 +152,7 @@ CPU4: cpu@400 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0 0x400>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> next-level-cache = <&L2_400>;
> power-domains = <&CPU_PD4>;
> @@ -167,6 +172,7 @@ CPU5: cpu@500 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0 0x500>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> next-level-cache = <&L2_500>;
> power-domains = <&CPU_PD5>;
> @@ -186,6 +192,7 @@ CPU6: cpu@600 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0 0x600>;
> + clocks = <&cpufreq_hw 1>;
> enable-method = "psci";
> next-level-cache = <&L2_600>;
> power-domains = <&CPU_PD6>;
> @@ -205,6 +212,7 @@ CPU7: cpu@700 {
> device_type = "cpu";
> compatible = "qcom,kryo";
> reg = <0 0x700>;
> + clocks = <&cpufreq_hw 2>;
> enable-method = "psci";
> next-level-cache = <&L2_700>;
> power-domains = <&CPU_PD7>;
> @@ -3341,6 +3349,7 @@ cpufreq_hw: cpufreq@17d91000 {
> <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>;
> interrupt-names = "dcvsh-irq-0", "dcvsh-irq-1", "dcvsh-irq-2";
> #freq-domain-cells = <1>;
> + #clock-cells = <1>;
> };
>
> pmu@24091000 {
