On Sun, 29 Jan 2023 at 14:01, Jonathan Neuschäfer <j.neuschaefer@xxxxxxx> wrote: > > This makes the text read a little better. > > Signed-off-by: Jonathan Neuschäfer <j.neuschaefer@xxxxxxx> Applied for next, thanks! Kind regards Uffe > --- > Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml > index dc6256f04b423..1c79b68753da0 100644 > --- a/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml > +++ b/Documentation/devicetree/bindings/mmc/fsl-imx-esdhc.yaml > @@ -98,7 +98,7 @@ properties: > Specify the number of delay cells for override mode. > This is used to set the clock delay for DLL(Delay Line) on override mode > to select a proper data sampling window in case the clock quality is not good > - due to signal path is too long on the board. Please refer to eSDHC/uSDHC > + because the signal path is too long on the board. Please refer to eSDHC/uSDHC > chapter, DLL (Delay Line) section in RM for details. > default: 0 > > @@ -127,7 +127,7 @@ properties: > Specify the increasing delay cell steps in tuning procedure. > The uSDHC use one delay cell as default increasing step to do tuning process. > This property allows user to change the tuning step to more than one delay > - cells which is useful for some special boards or cards when the default > + cell which is useful for some special boards or cards when the default > tuning step can't find the proper delay window within limited tuning retries. > default: 0 > > -- > 2.39.0 >
