On Wed, Feb 8, 2023 at 6:45 PM AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> wrote: > > We finally have working GPU DVFS on MediaTek SoCs. > On Panfrost. > For real. > ...and the best part is that it's going upstream. > > In order to get GPU DVFS working, it was necessary to satisfy a > specific constraint (which is different, depending on the SoC) > between two regulators: GPU VCORE and GPU SRAM. > This was done through adding the mtk-regulator-coupler driver, > which transparently manages the voltage relation between these > two vregs, hence completely eliminating the need to manage these > regulators in the Panfrost driver; this solves the long standing > issue with devfreq+opp tables not supporting managing voltages > for two regulators per opp entry out of the box, due to which > we never got GPU DVFS on those SoCs, often locking them out to > a low GPU frequency. > > This changes. Right now! > > Tested on MT8192, MT8195 Chromebooks. > > This series depends on [1]. > > [1]: https://lore.kernel.org/lkml/20230208103709.116896-1-angelogioacchino.delregno@xxxxxxxxxxxxx/ Whole series is Tested-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx> Tested on MT8183 Juniper (Kukui-based device), MT8192 Hayato (Asurada-based), and MT8195 Tomato (Cherry-based). GPU probed. When running glmark-es2-drm, observed state transitions in /sys/class/devfreq/13040000.gpu/trans_stat , as well as actual changes to values for regulators and clocks. Also observed that sometimes when glmark terminated, the GPU would not be brought down to the lowest OPP.
