On 07/02/2023 16:27, Dmitry Baryshkov wrote: > On 07/02/2023 15:35, Neil Armstrong wrote: >> On 07/02/2023 11:32, Dmitry Baryshkov wrote: >>> On 07/02/2023 12:03, Neil Armstrong wrote: >>>> Recents SoCs like the SM8450 or SM8550 requires memory interconnect >>>> in order to have functional DMA. >>>> >>>> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx> >>>> --- >>>> Documentation/devicetree/bindings/dma/qcom,bam-dma.yaml | 6 ++++++ >>>> 1 file changed, 6 insertions(+) >>> >>> I suspect this will not work without a change for a driver. >>> >> >> I had the impression single interconnect entries would be taken in account >> by the platform core, but it doesn't seem to be the case, anyway I can;t >> find >> any code doing that. > > Probably you mixed interconnects and power-domains here. > The driver change was submitted some time ago: https://lore.kernel.org/all/20210505213731.538612-10-bhupesh.sharma@xxxxxxxxxx/ There is already DTS user of it and we expect driver to be resubmitted at some point. What I don't really get is that crypto driver sets bandwidth for interconnects, not the BAM. Why BAM needs interconnect? Usually you do not need to initialize some middle paths. Getting the final interconnect path (e.g. crypto-memory) is enough, because it includes everything in between. Maybe my review tag was a bit premature... Best regards, Krzysztof
