This series is based on the existing upstream work from Sebastian Reichel: https://git.kernel.org/pub/scm/linux/kernel/git/sre/linux-misc.git/log/?h=rk3588 And I'm a completely newbie to arm64 world, thus if there is something wrong, feel free to point out and I'm pretty happy to learn from the failure. [BACKGROUND] RK3588S and RK3588 have PCIE supports, it's done by the following 3 controllers: - PCIE2.0x1 lane @fe180000 (both RK3588S and RK3588) - PCIE2.0x1 lane @fe190000 (both RK3588S and RK3588) Thes two are all connected to a naneng combo phy each, normally shared with SATA or USB. - PCIE2.0x1 lane @fe170000 (RK3588 exlusive) This one is also connected to a naneng combo phy, normally shared with SATA or USB. - PCIE3.0x4 lanes @fe15000 (RK3588 exclusive) And unlike other boards, ROCK5B is utilizing PCIE extensively, its network controller (RTL8125 2.5Gbps Ethernet) is connected to the PCIE2.0 lane at fe190000, and an M.2 slot is attached to the PCIE3.0x4 lanes. [WORKING] Currently the series is able to bring up the PCIE3.0x4 lanes and properly boot from an NVME at that M.2 slot of Rock5B boards. [NOT WORKING] All PCIE2.0 lanes connected to naneng combo phy are not working. I tried forward porting the extra handling from downstream, but it only results hanging at probing (causing RCU stall). [EXTRA WANRING] - PCI MSI initialization warning WARNING: CPU: 7 PID: 1 at drivers/pci/msi/msi.h:121 pci_msi_setup_msi_irqs+0x38/0x4c This seems to be caused by the fact that we are still using legcacy msi irqs? I checked up the gic and its dts, can not figure out why (all pretty the same just like rk3399 and rk3568). Any help would be appreciated. - pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-0f] (conflicts with (null) [bus 00-0f]) The vendoer kernel also has this problem, but my RK3399 board with upstream kernel didn't trigger this at all, but something else like: pci 0000:00:00.0: bridge configuration invalid ([bus 00-00]), reconfiguring Then: pci_bus 0000:01: busn_res: [bus 01-1f] end is updated to 01 Not sure if it's something missing or can be just ignored. [PCI DMESG] With this patchset, the PCI initialization and nvme would look like this: [ 0.142984] rockchip-dw-pcie fe150000.pcie: host bridge /pcie@fe150000 ranges: [ 0.143653] rockchip-dw-pcie fe150000.pcie: IO 0x00f0100000..0x00f01fffff -> 0x00f0100000 [ 0.144463] rockchip-dw-pcie fe150000.pcie: MEM 0x00f0200000..0x00f0ffffff -> 0x00f0200000 [ 0.145261] rockchip-dw-pcie fe150000.pcie: MEM 0x0900000000..0x093fffffff -> 0x0900000000 [ 0.154022] rockchip-dw-pcie fe150000.pcie: iATU: unroll T, 8 ob, 8 ib, align 64K, limit 8G [ 0.360415] rockchip-dw-pcie fe150000.pcie: PCIe Gen.3 x4 link up [ 0.361099] rockchip-dw-pcie fe150000.pcie: PCI host bridge to bus 0000:00 [ 0.361731] pci_bus 0000:00: root bus resource [bus 00-0f] [ 0.362236] pci_bus 0000:00: root bus resource [io 0x0000-0xfffff] (bus address [0xf0100000-0xf01fffff]) [ 0.363113] pci_bus 0000:00: root bus resource [mem 0xf0200000-0xf0ffffff] [ 0.363744] pci_bus 0000:00: root bus resource [mem 0x900000000-0x93fffffff pref] [ 0.364450] pci 0000:00:00.0: [1d87:3588] type 01 class 0x060400 [ 0.365005] pci 0000:00:00.0: reg 0x10: [mem 0x00000000-0x3fffffff] [ 0.365583] pci 0000:00:00.0: reg 0x14: [mem 0x00000000-0x3fffffff] [ 0.366159] pci 0000:00:00.0: reg 0x38: [mem 0x00000000-0x0000ffff pref] [ 0.366801] pci 0000:00:00.0: supports D1 D2 [ 0.367193] pci 0000:00:00.0: PME# supported from D0 D1 D3hot [ 0.368647] pci_bus 0000:01: busn_res: can not insert [bus 01-ff] under [bus 00-0f] (conflicts with (null) [bus 00-0f]) [ 0.369681] pci 0000:01:00.0: [1d97:5216] type 00 class 0x010802 [ 0.370277] pci 0000:01:00.0: reg 0x10: [mem 0x00000000-0x0000ffff 64bit] [ 0.370975] pci 0000:01:00.0: reg 0x30: [mem 0x00000000-0x0001ffff pref] [ 0.372130] pci 0000:00:00.0: BAR 0: no space for [mem size 0x40000000] [ 0.372742] pci 0000:00:00.0: BAR 0: failed to assign [mem size 0x40000000] [ 0.373381] pci 0000:00:00.0: BAR 1: no space for [mem size 0x40000000] [ 0.373988] pci 0000:00:00.0: BAR 1: failed to assign [mem size 0x40000000] [ 0.374628] pci 0000:00:00.0: BAR 14: assigned [mem 0xf0200000-0xf02fffff] [ 0.375259] pci 0000:00:00.0: BAR 6: assigned [mem 0xf0300000-0xf030ffff pref] [ 0.375923] pci 0000:01:00.0: BAR 6: assigned [mem 0xf0200000-0xf021ffff pref] [ 0.376590] pci 0000:01:00.0: BAR 0: assigned [mem 0xf0220000-0xf022ffff 64bit] [ 0.377281] pci 0000:00:00.0: PCI bridge to [bus 01-ff] [ 0.377762] pci 0000:00:00.0: bridge window [mem 0xf0200000-0xf02fffff] [ 0.426841] pcieport 0000:00:00.0: PME: Signaling with IRQ 33 [ 0.427487] pcieport 0000:00:00.0: AER: enabled with IRQ 33 [ 0.625353] nvme nvme0: pci function 0000:01:00.0 [ 0.625774] nvme 0000:01:00.0: enabling device (0000 -> 0002) [ 0.717069] nvme nvme0: Shutdown timeout set to 8 seconds [ 0.723025] nvme nvme0: allocated 64 MiB host memory buffer. [ 0.816820] nvme nvme0: 1/0/0 default/read/poll queues [ 0.818079] sdhci-pltfm: SDHCI platform and OF driver helper [ 0.820678] nvme0n1: p1 p2 Qu Wenruo (5): drivers: phy: rockhip: remove 24M and 25M clock handling for naneng combphy dt-bindings: pci: controller: add pcie controller binding for RK3588 drivers: pci: controller: add PCIE controller driver for RK3588 arm64: dts: rockchip: add PCIE3 controller and phy for RK3588 arm64: dts: rockchip: enable PCIE3 controller and phy for Rock5B boards .../bindings/pci/rockchip-dw-pcie.yaml | 5 +- .../boot/dts/rockchip/rk3588-rock-5b.dts | 22 +++ arch/arm64/boot/dts/rockchip/rk3588.dtsi | 128 ++++++++++++++++++ arch/arm64/boot/dts/rockchip/rk3588s.dtsi | 16 +++ drivers/pci/controller/dwc/pcie-dw-rockchip.c | 1 + .../rockchip/phy-rockchip-naneng-combphy.c | 17 --- 6 files changed, 170 insertions(+), 19 deletions(-) -- 2.39.1
