On Thu, Jan 19, 2023 at 8:50 PM Garmin.Chang <Garmin.Chang@xxxxxxxxxxxx> wrote:
>
> Add MT8188 ccusys clock controller which provides clock gate
> control in Camera Computing Unit.
If this is also for camera related functions, could you fold this into
the previous CAM clock driver? That would save a bit of space.
The code looks OK.
Reviewed-by: Chen-Yu Tsai <wenst@xxxxxxxxxxxx>
> Signed-off-by: Garmin.Chang <Garmin.Chang@xxxxxxxxxxxx>
> ---
> drivers/clk/mediatek/Makefile | 2 +-
> drivers/clk/mediatek/clk-mt8188-ccu.c | 48 +++++++++++++++++++++++++++
> 2 files changed, 49 insertions(+), 1 deletion(-)
> create mode 100644 drivers/clk/mediatek/clk-mt8188-ccu.c
>
> diff --git a/drivers/clk/mediatek/Makefile b/drivers/clk/mediatek/Makefile
> index dc247bf67e8b..dbd140b81763 100644
> --- a/drivers/clk/mediatek/Makefile
> +++ b/drivers/clk/mediatek/Makefile
> @@ -85,7 +85,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-mcu.o clk-mt8186-topckgen.o clk-mt
> clk-mt8186-cam.o clk-mt8186-mdp.o clk-mt8186-ipe.o
> obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-mt8188-topckgen.o \
> clk-mt8188-peri_ao.o clk-mt8188-infra_ao.o \
> - clk-mt8188-cam.o
> + clk-mt8188-cam.o clk-mt8188-ccu.o
> obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> diff --git a/drivers/clk/mediatek/clk-mt8188-ccu.c b/drivers/clk/mediatek/clk-mt8188-ccu.c
> new file mode 100644
> index 000000000000..b7380060f906
> --- /dev/null
> +++ b/drivers/clk/mediatek/clk-mt8188-ccu.c
> @@ -0,0 +1,48 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +//
> +// Copyright (c) 2022 MediaTek Inc.
> +// Author: Garmin Chang <garmin.chang@xxxxxxxxxxxx>
> +
> +#include <linux/clk-provider.h>
> +#include <linux/platform_device.h>
> +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> +
> +#include "clk-gate.h"
> +#include "clk-mtk.h"
> +
> +static const struct mtk_gate_regs ccu_cg_regs = {
> + .set_ofs = 0x4,
> + .clr_ofs = 0x8,
> + .sta_ofs = 0x0,
> +};
> +
> +#define GATE_CCU(_id, _name, _parent, _shift) \
> + GATE_MTK(_id, _name, _parent, &ccu_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
> +
> +static const struct mtk_gate ccu_clks[] = {
> + GATE_CCU(CLK_CCU_LARB27, "ccu_larb27", "top_ccu", 0),
> + GATE_CCU(CLK_CCU_AHB, "ccu_ahb", "top_ccu", 1),
> + GATE_CCU(CLK_CCU_CCU0, "ccu_ccu0", "top_ccu", 2),
> +};
> +
> +static const struct mtk_clk_desc ccu_desc = {
> + .clks = ccu_clks,
> + .num_clks = ARRAY_SIZE(ccu_clks),
> +};
> +
> +static const struct of_device_id of_match_clk_mt8188_ccu[] = {
> + { .compatible = "mediatek,mt8188-ccusys", .data = &ccu_desc},
> + { /* sentinel */ }
> +};
> +
> +static struct platform_driver clk_mt8188_ccu_drv = {
> + .probe = mtk_clk_simple_probe,
> + .remove = mtk_clk_simple_remove,
> + .driver = {
> + .name = "clk-mt8188-ccu",
> + .of_match_table = of_match_clk_mt8188_ccu,
> + },
> +};
> +
> +builtin_platform_driver(clk_mt8188_ccu_drv);
> +MODULE_LICENSE("GPL");
> --
> 2.18.0
>
>
