On Wed, 28 Dec 2022 22:48:43 +0000, Conor Dooley wrote:
> Hey,
>
> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@xxxxxxxx>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx>
>> Co-developed-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
>> Signed-off-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
>> Co-developed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
>> Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>> 1 file changed, 411 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..64d260ea1f29
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -0,0 +1,411 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@xxxxxxxx>
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> +/ {
>> + compatible = "starfive,jh7110";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + S76_0: cpu@0 {
>> + compatible = "sifive,u74-mc", "riscv";
>
> The label here says S76 but the compatible says u74-mc.
U74-MC has 5 cores including 1 * S7 core and 4 * U74 cores.
> Which is correct? Your docs say S7 and S76, so I would imagine that it
> is actually an S76?
I found SiFive website [1] call it S76, but call it S7 in other places.
So I misunderstood this. Considering the ISA difference you described
as below, I think it's proper to change the label to "S7_0".
[1] https://www.sifive.com/cores/essential
>
>> + reg = <0>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <8192>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <16384>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imac";
>
> While I was poking around trying to see if there was some logic behind
> that compatible, I noticed that SiFive's docs for the S76 say it is
> RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
> I assume that rv64imac is the correct one here?
Yes, "RV64IMAC" is correct. The monitor core in U74-MC is a
S7-series core, not S76.
>
>> + tlb-split;
>> + status = "disabled";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_1: cpu@1 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <1>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>
> That also begs the question:
> Do your u74s support RV64GBC, as the (current) SiFive documentation
> suggests?
Actually, U74 doesn't support the full B extension, and the SiFive doc [1]
describes the ISA of U74 is "RV64GC_Zba_Zbb_Sscofpmf" which "G" includes
"IMAFD". "_Zba_Zbb_Sscofpmf" is not shown in other device trees such as
jh7100.dtsi and fu740-c000.dtsi, so I didn't show them here.
[1] https://sifive.cdn.prismic.io/sifive/2dd11994-693c-4360-8aea-5453d8642c42_u74mc_core_complex_manual_21G3.pdf
Best regards,
Hal
