On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
---
arch/arm/boot/dts/imx6dl-alti6p.dts | 12 ++++++++----
1 file changed, 8 insertions(+), 4 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-alti6p.dts b/arch/arm/boot/dts/imx6dl-alti6p.dts
index e8325fd680d9..e6a4e2770640 100644
--- a/arch/arm/boot/dts/imx6dl-alti6p.dts
+++ b/arch/arm/boot/dts/imx6dl-alti6p.dts
@@ -22,6 +22,7 @@ clock_ksz8081: clock-ksz8081 {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
i2c2-mux {
@@ -191,6 +192,13 @@ &can1 {
status = "okay";
};
+&clks {
+ clocks = <&clock_ksz8081>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&clock_ksz8081>;
+};
+
&ecspi1 {
cs-gpios = <&gpio3 19 GPIO_ACTIVE_LOW>;
pinctrl-names = "default";
@@ -208,10 +216,6 @@ &fec {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_enet>;
phy-mode = "rmii";
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&clock_ksz8081>;
- clock-names = "ipg", "ahb", "ptp";
status = "okay";
mdio {
--
2.30.2
