Hi Krzysztof,
---- On Fri, 27 Jan 2023 23:08:09 +0800 Krzysztof Kozlowski wrote ---
> On 27/01/2023 15:48, Li Chen wrote:
> > >
> > > but what you are saying is that there is no separate clock controller
> > > device with its own IO address but these clocks are part of rct_syscon.
> > > Then model it that way in DTS. The rct_syscon is then your clock
> > > controller and all these fake gclk-core and gclk-ddr nodes should be gone.
> >
> > Ok, I will remove these fake nodes, and model the hardware as:
> >
> > rct_syscon node
> > | clock node(pll, div, mux, composite clocks live in the same driver)
> > | other periphal nodes
>
> You need clock node if it takes any resources. If it doesn't, you do not
> need it.
Got it, I will model it as:
rct_syscon(compatible include "ambarella, <SoC>-clock"...)
| peripheral A
| peripheral B
| ...
One more question, two driver models:
a. compatible = "ambarella, <SoC>-clock", handle all clocks(pll, div, mux, composite) in single driver.
b. compatible = "ambarella, <SoC>-pll-clock", "ambarella, <SoC>-composite-clock", "ambarella, <SoC>-div-clock"......
and implement a driver for each of them.
Which driver model is preferred?
Regards,
Li
