Quoting Dmitry Baryshkov (2023-01-26 15:03:19) > diff --git a/drivers/clk/qcom/apcs-msm8996.c b/drivers/clk/qcom/apcs-msm8996.c > new file mode 100644 > index 000000000000..48d22572b6ae > --- /dev/null > +++ b/drivers/clk/qcom/apcs-msm8996.c > @@ -0,0 +1,88 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * Qualcomm APCS clock controller driver > + * [...] > + > + /* > + * This clock is used during CPU cluster setup while setting up CPU PLLs. > + * Add hardware mandated delay to make sure that the sys_apcs_aux clock > + * is stable (after setting the divider) before continuing > + * bootstrapping to keep CPUs from ending up in a weird state. > + */ > + udelay(5); > + > + /* > + * As this clocks is a parent of the CPU cluster clocks and is actually > + * used as a parent during CPU clocks setup, we want for it to gegister s/gegister/register/ > + * as early as possible, without letting fw_devlink to delay probing of > + * either of the drivers. Ok, good to know fw_devlink is the problem in this case. > + * > + * The sys_apcs_aux is a child (divider) of gpll0, but we register it > + * as a fixed rate clock instead to ease bootstrapping procedure. By > + * doing this we make sure that CPU cluster clocks are able to be setup > + * early during the boot process (as it is recommended by Qualcomm). > + */ > + hw = devm_clk_hw_register_fixed_rate(dev, "sys_apcs_aux", NULL, 0, 300000000); > + if (IS_ERR(hw)) > + return PTR_ERR(hw); > +
