Thanks for taking time to review the patch!
On 1/13/2023 8:35 PM, Konrad Dybcio wrote:
On 13.01.2023 15:36, devi priya wrote:
Add schema for primary CPU PLL found on few Qualcomm platforms.
Co-developed-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>
Signed-off-by: Praveenkumar I <quic_ipkumar@xxxxxxxxxxx>
Signed-off-by: devi priya <quic_devipriy@xxxxxxxxxxx>
---
Doesn't this belong in Documentation/devicetree/bindings/clock/qcom,a53pll.yaml?
It looks identical, so it may be as simple as adding your
new compatible there..
As the name was specific to a53pll, added a new yaml for a73.
Will add the a73 compatible in qcom,a53pll.yaml if that's accepted!
Konrad
.../bindings/clock/qcom,a73pll.yaml | 52 +++++++++++++++++++
1 file changed, 52 insertions(+)
create mode 100644 Documentation/devicetree/bindings/clock/qcom,a73pll.yaml
diff --git a/Documentation/devicetree/bindings/clock/qcom,a73pll.yaml b/Documentation/devicetree/bindings/clock/qcom,a73pll.yaml
new file mode 100644
index 000000000000..a0e81094db8d
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/qcom,a73pll.yaml
@@ -0,0 +1,52 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,a73pll.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm A73 PLL clock
+
+maintainers:
+ - Bjorn Andersson <andersson@xxxxxxxxxx>
+
+description:
+ The A73 PLL on few Qualcomm platforms is the main CPU PLL used for
+ frequencies above 1GHz.
+
+properties:
+ compatible:
+ enum:
+ - qcom,ipq9574-a73pll
+
+ reg:
+ maxItems: 1
+
+ '#clock-cells':
+ const: 0
+
+ clocks:
+ items:
+ - description: board XO clock
+
+ clock-names:
+ items:
+ - const: xo
+
+ operating-points-v2: true
+
+required:
+ - compatible
+ - reg
+ - '#clock-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ a73pll: clock@b116000 {
+ compatible = "qcom,ipq9574-a73pll";
+ reg = <0x0b116000 0x40>;
+ #clock-cells = <0>;
+ clocks = <&xo_board_clk>;
+ clock-names = "xo";
+ };
Best Regards,
Devi Priya
