On 23-01-27 12:51:05, Krzysztof Kozlowski wrote:
> On 26/01/2023 13:46, Abel Vesa wrote:
> > Add USB host controller and PHY nodes.
> >
> > Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> > ---
> >
> > NOTE: This patch has been already merged. It is here only to provide
> > context for the rest of the patchset. There is a change with respect to the
> > clocks, but that will be sent as a separate/individual fix patch.
> >
> > arch/arm64/boot/dts/qcom/sm8550.dtsi | 92 +++++++++++++++++++++++++++-
> > 1 file changed, 91 insertions(+), 1 deletion(-)
> >
> > diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > index 4daf1f03d79f..6801454bbe10 100644
> > --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> > @@ -13,6 +13,7 @@
> > #include <dt-bindings/mailbox/qcom-ipcc.h>
> > #include <dt-bindings/power/qcom-rpmpd.h>
> > #include <dt-bindings/soc/qcom,rpmh-rsc.h>
> > +#include <dt-bindings/phy/phy-qcom-qmp.h>
> > #include <dt-bindings/thermal/thermal.h>
> >
> > / {
> > @@ -652,7 +653,7 @@ gcc: clock-controller@100000 {
> > <&ufs_mem_phy 0>,
> > <&ufs_mem_phy 1>,
> > <&ufs_mem_phy 2>,
> > - <0>;
> > + <&usb_dp_qmpphy QMP_USB43DP_USB3_PIPE_CLK>;
> > };
> >
> > ipcc: mailbox@408000 {
> > @@ -1924,6 +1925,95 @@ opp-202000000 {
> > };
> > };
> >
> > + usb_1_hsphy: phy@88e3000 {
> > + compatible = "qcom,sm8550-snps-eusb2-phy";
> > + reg = <0x0 0x088e3000 0x0 0x154>;
> > + #phy-cells = <0>;
> > +
> > + clocks = <&tcsr TCSR_USB2_CLKREF_EN>;
> > + clock-names = "ref";
> > +
> > + resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + usb_dp_qmpphy: phy@88e8000 {
> > + compatible = "qcom,sm8550-qmp-usb3-dp-phy";
> > + reg = <0x0 0x088e8000 0x0 0x3000>;
> > +
> > + clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> > + <&rpmhcc RPMH_CXO_CLK>,
> > + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> > + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> > + clock-names = "aux", "ref", "com_aux", "usb3_pipe";
> > +
> > + power-domains = <&gcc USB3_PHY_GDSC>;
> > +
> > + resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> > + <&gcc GCC_USB3_PHY_PRIM_BCR>;
> > + reset-names = "phy", "common";
> > +
> > + #clock-cells = <1>;
> > + #phy-cells = <1>;
> > +
> > + status = "disabled";
> > + };
> > +
> > + usb_1: usb@a6f8800 {
> > + compatible = "qcom,sm8550-dwc3", "qcom,dwc3";
> > + reg = <0x0 0x0a6f8800 0x0 0x400>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
> > + ranges;
> > +
> > + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>,
> > + <&gcc GCC_USB30_PRIM_MASTER_CLK>,
> > + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>,
> > + <&gcc GCC_USB30_PRIM_SLEEP_CLK>,
> > + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> > + <&rpmhcc TCSR_USB3_CLKREF_EN>;
> > + clock-names = "cfg_noc",
> > + "core",
> > + "iface",
> > + "sleep",
> > + "mock_utmi",
> > + "xo";
> > +
> > + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>,
> > + <&gcc GCC_USB30_PRIM_MASTER_CLK>;
> > + assigned-clock-rates = <19200000>, <200000000>;
> > +
> > + interrupts-extended = <&intc GIC_SPI 130 IRQ_TYPE_LEVEL_HIGH>,
> > + <&pdc 17 IRQ_TYPE_LEVEL_HIGH>,
> > + <&pdc 15 IRQ_TYPE_EDGE_RISING>,
> > + <&pdc 14 IRQ_TYPE_EDGE_RISING>;
> > + interrupt-names = "hs_phy_irq",
> > + "ss_phy_irq",
> > + "dm_hs_phy_irq",
> > + "dp_hs_phy_irq";
> > +
> > + power-domains = <&gcc USB30_PRIM_GDSC>;
> > + required-opps = <&rpmhpd_opp_nom>;
>
> This part was merged but it is not correct without [1]. Are we going to
> revive [1] or should we drop it?
Well, but this one has been merged as well for sc8280xp:
https://lore.kernel.org/all/20230112135117.3836655-1-quic_bjorande@xxxxxxxxxxx/
>
> [1] https://lore.kernel.org/all/YXcBK7zqny0s4gd4@ripper/
>
> Best regards,
> Krzysztof
>
