On Thu, Jan 26, 2023 at 11:48:53AM -0500, Sean Anderson wrote: > On 1/25/23 18:43, Shawn Guo wrote: > > On Thu, Dec 29, 2022 at 07:01:36PM -0500, Sean Anderson wrote: > >> This adds appropriate bindings for the macs which use the SerDes. The > >> 156.25MHz fixed clock is a crystal. The 100MHz clocks (there are > >> actually 3) come from a Renesas 6V49205B at address 69 on i2c0. There is > >> no driver for this device (and as far as I know all you can do with the > >> 100MHz clocks is gate them), so I have chosen to model it as a single > >> fixed clock. > >> > >> Note: the SerDes1 lane numbering for the LS1046A is *reversed*. > >> This means that Lane A (what the driver thinks is lane 0) uses pins > >> SD1_TX3_P/N. > >> > >> Because this will break ethernet if the serdes is not enabled, enable > >> the serdes driver by default on Layerscape. > >> > >> Signed-off-by: Sean Anderson <sean.anderson@xxxxxxxx> > >> --- > >> This depends on [1]. > >> > >> [1] https://lore.kernel.org/netdev/20220804194705.459670-4-sean.anderson@xxxxxxxx/ > >> > >> Changes in v9: > >> - Fix name of phy mode node > >> - phy-type -> fsl,phy > >> > >> Changes in v8: > >> - Rename serdes phy handles to use _A, _B, etc. instead of _0, _1, etc. > >> This should help remind readers that the numbering corresponds to the > >> physical layout of the registers, and not the lane (pin) number. > >> > >> Changes in v6: > >> - XGI.9 -> XFI.9 > >> > >> Changes in v4: > >> - Convert to new bindings > >> > >> .../boot/dts/freescale/fsl-ls1046a-rdb.dts | 112 ++++++++++++++++++ > >> drivers/phy/freescale/Kconfig | 1 + > > > > The phy driver Kconfig change shouldn't be part of this patch. > > I put it here for bisectability, since this is the point where we need > to enable it. But I can do this in a separate patch if you want. >From DT ABI perspective, it's already broken anyway if you need to change kernel and DT atomically. Shawn
