On 26/01/2023 09:44, Heiner Kallweit wrote:
On 26.01.2023 08:57, Neil Armstrong wrote:
Hi Heiner,
On 25/01/2023 08:00, Heiner Kallweit wrote:
SDIO specification defines that the interrupt is level-sensitive.
Fix the interrupt trigger type for emmc_a accordingly.
See comment at beginning of the file wrt which is the SDIO port.
mmc2 = &sd_emmc_a; /* SDIO */
The usage of edge-triggered interrupts lead to lost interrupts under load,
see [0]. This was confirmed to be fixed by using level-triggered
interrupts.
Note:
SDIO interrupt support was added in Linux just recently, however other
users of this dts may be affected too.
Switching from edge to level has already fixed performance issues on ethernet,
so I think this would be the right direction, but since the SDIO, eMMC and SD controllers
are basically the same IP, they should have the same interrupt setup.
It makes no sense to have level only for SDIO, so perhaps it would be right to
switch every controllers to LEVEL (including AXG) and test to see if there's no regressions.
After thinking a minute about it I think you're right. I tested on my system and
see no difference in behavior no matter whether emmc interrupt is level or edge.
Do you want to make further tests on your test systems?
And I'm wondering whether there's stronger evidence than just testing which trigger
type works better. Don't the datasheets give a hint?
Nop the datasheet doesn't help here at all, I can totally apply a patch you send on
my for-next branch for testing and see if it breaks something on the various CIs running
on linux-next.
I'd say all interrupts are level on amlogic SoCs, mainly because the interrupt signal
stays high until we clear all the status bits, but the way we design the interrupt
handler works with both.
In edge, you get the interrupt event on a transition from low to high, so if you miss
an interrupt status that arrives between the time you read the status and you clear it,
you'll totally miss it and probably all future events.
On level, the interrupt handler will fire until the status bits are not cleared, so you
can't miss an interrupt.
The way Amlogic designs their interrupts mask/clear/status matches the level setup.
So provide a patch changing the mmc controller's trigger type, and I'll push it to
linux-next for testing.
Neil
Neil
[0] https://www.spinics.net/lists/linux-mmc/msg73991.html
Fixes: 1499218c80c9 ("arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi")
Reported-by: Peter Suti <peter.suti@xxxxxxxxxxxxxxxxxxx>
Tested-by: Peter Suti <peter.suti@xxxxxxxxxxxxxxxxxxx>
Cc: stable@xxxxxxxxxxxxxxx
Signed-off-by: Heiner Kallweit <hkallweit1@xxxxxxxxx>
---
v2:
- rebase considering recent node name change sd -> mmc for sd_emmc_a
---
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-gx.dtsi | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
index 1a931d5c2..c09eb9f6f 100644
--- a/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi
@@ -2324,7 +2324,7 @@ uart_A: serial@24000 {
sd_emmc_a: mmc@ffe03000 {
compatible = "amlogic,meson-axg-mmc";
reg = <0x0 0xffe03000 0x0 0x800>;
- interrupts = <GIC_SPI 189 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
clocks = <&clkc CLKID_SD_EMMC_A>,
<&clkc CLKID_SD_EMMC_A_CLK0>,
diff --git a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
index a79a35e84..ae1a5a568 100644
--- a/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
+++ b/arch/arm64/boot/dts/amlogic/meson-gx.dtsi
@@ -603,7 +603,7 @@ apb: apb@d0000000 {
sd_emmc_a: mmc@70000 {
compatible = "amlogic,meson-gx-mmc", "amlogic,meson-gxbb-mmc";
reg = <0x0 0x70000 0x0 0x800>;
- interrupts = <GIC_SPI 216 IRQ_TYPE_EDGE_RISING>;
+ interrupts = <GIC_SPI 216 IRQ_TYPE_LEVEL_HIGH>;
status = "disabled";
};
