Quoting Konrad Dybcio (2023-01-25 14:05:27) > > On 25.01.2023 22:56, Stephen Boyd wrote: > > > > So it is waiting for the CPU clk to be stable? The comment is not clear. > Okay, so perhaps this is just a misunderstanding because of a lackluster > comment.. This SYS_APCS_AUX (provided by this driver) is one of the CPU > clock sources (and probably the "safest" of them all, as it's fed by > GPLL0 and not the CPU PLLs) the delay is there to ensure it can > stabilize after setting the divider to DIV2. In a theoretical case, the > big 8996 cpucc driver could select this clock as a target for one (or > both) of the per-cluster muxes and it could put the CPUs in a weird state. > > As unlikely as that would be, especially considering 8996 (AFAIK) doesn't > use this clock source coming out of reset / bootloader, this lets us > ensure one less thing can break. Great! I look forward to a better comment.
