Quoting Dmitry Baryshkov (2023-01-10 22:03:51)
> Define clock/clock-names properties of the GCC device node to be used
> on APQ8084 platform.
>
> Note: the driver uses a single pcie_pipe clock, however most probably
> there are two pipe clocks, one from each of PCIe QMP PHYs.
>
> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Stephen Boyd <sboyd@xxxxxxxxxx>
> diff --git a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> index 8ade176c24f4..d84608269080 100644
> --- a/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> +++ b/Documentation/devicetree/bindings/clock/qcom,gcc-apq8084.yaml
> @@ -32,11 +56,31 @@ unevaluatedProperties: false
>
> examples:
> - |
> + /* UFS PHY on APQ8084 is not supported (yet), so these bindings just serve an example */
This comment will go out of date and probably nobody will notice. Just
remove it?
> clock-controller@fc400000 {
> compatible = "qcom,gcc-apq8084";
> reg = <0xfc400000 0x4000>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> #power-domain-cells = <1>;
