On 23.01.2023 14:29, Luca Weiss wrote:
> The sc7180 phy compatible works fine for some cases, but it turns out
> sm6350 does need proper phy configuration in the driver, so use the
> newly added sm6350 compatible.
>
> Because the sm6350 compatible is using the new binding, we need to
> change the node quite a bit to match it.
>
> This fixes qmpphy init when no USB cable is plugged in during bootloader
> stage.
>
> Reviewed-by: Johan Hovold <johan+linaro@xxxxxxxxxx>
> Signed-off-by: Luca Weiss <luca.weiss@xxxxxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> arch/arm64/boot/dts/qcom/sm6350.dtsi | 54 +++++++++++-------------------------
> 1 file changed, 16 insertions(+), 38 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm6350.dtsi b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> index 8224adb99948..128dbbe23ef5 100644
> --- a/arch/arm64/boot/dts/qcom/sm6350.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm6350.dtsi
> @@ -13,6 +13,7 @@
> #include <dt-bindings/interconnect/qcom,sm6350.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/phy/phy-qcom-qmp.h>
> #include <dt-bindings/power/qcom-rpmpd.h>
> #include <dt-bindings/soc/qcom,rpmh-rsc.h>
>
> @@ -1314,49 +1315,26 @@ usb_1_hsphy: phy@88e3000 {
> resets = <&gcc GCC_QUSB2PHY_PRIM_BCR>;
> };
>
> - usb_1_qmpphy: phy@88e9000 {
> - compatible = "qcom,sc7180-qmp-usb3-dp-phy";
> - reg = <0 0x088e9000 0 0x200>,
> - <0 0x088e8000 0 0x40>,
> - <0 0x088ea000 0 0x200>;
> - status = "disabled";
> - #address-cells = <2>;
> - #size-cells = <2>;
> - ranges;
> + usb_1_qmpphy: phy@88e8000 {
> + compatible = "qcom,sm6350-qmp-usb3-dp-phy";
> + reg = <0 0x088e8000 0 0x3000>;
>
> clocks = <&gcc GCC_USB3_PRIM_PHY_AUX_CLK>,
> - <&xo_board>,
> - <&rpmhcc RPMH_QLINK_CLK>,
> - <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>;
> - clock-names = "aux", "cfg_ahb", "ref", "com_aux";
> + <&gcc GCC_USB3_PRIM_CLKREF_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_COM_AUX_CLK>,
> + <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> + clock-names = "aux", "ref", "com_aux", "usb3_pipe";
> +
> + power-domains = <&gcc USB30_PRIM_GDSC>;
>
> - resets = <&gcc GCC_USB3_DP_PHY_PRIM_BCR>,
> - <&gcc GCC_USB3_PHY_PRIM_BCR>;
> + resets = <&gcc GCC_USB3_PHY_PRIM_BCR>,
> + <&gcc GCC_USB3_DP_PHY_PRIM_BCR>;
> reset-names = "phy", "common";
>
> - usb_1_ssphy: usb3-phy@88e9200 {
> - reg = <0 0x088e9200 0 0x200>,
> - <0 0x088e9400 0 0x200>,
> - <0 0x088e9c00 0 0x400>,
> - <0 0x088e9600 0 0x200>,
> - <0 0x088e9800 0 0x200>,
> - <0 0x088e9a00 0 0x100>;
> - #clock-cells = <0>;
> - #phy-cells = <0>;
> - clocks = <&gcc GCC_USB3_PRIM_PHY_PIPE_CLK>;
> - clock-names = "pipe0";
> - clock-output-names = "usb3_phy_pipe_clk_src";
> - };
> + #clock-cells = <1>;
> + #phy-cells = <1>;
>
> - dp_phy: dp-phy@88ea200 {
> - reg = <0 0x088ea200 0 0x200>,
> - <0 0x088ea400 0 0x200>,
> - <0 0x088eaa00 0 0x200>,
> - <0 0x088ea600 0 0x200>,
> - <0 0x088ea800 0 0x200>;
> - #phy-cells = <0>;
> - #clock-cells = <1>;
> - };
> + status = "disabled";
> };
>
> dc_noc: interconnect@9160000 {
> @@ -1430,7 +1408,7 @@ usb_1_dwc3: usb@a600000 {
> snps,dis_enblslpm_quirk;
> snps,has-lpm-erratum;
> snps,hird-threshold = /bits/ 8 <0x10>;
> - phys = <&usb_1_hsphy>, <&usb_1_ssphy>;
> + phys = <&usb_1_hsphy>, <&usb_1_qmpphy QMP_USB43DP_USB3_PHY>;
> phy-names = "usb2-phy", "usb3-phy";
> };
> };
>
