On Sat, Jan 21, 2023, Krishna Kurapati PSSNV wrote:
>
>
> On 1/21/2023 7:49 AM, Thinh Nguyen wrote:
> > On Sat, Jan 21, 2023, Krishna Kurapati PSSNV wrote:
> > >
> > >
> > > On 1/21/2023 4:27 AM, Thinh Nguyen wrote:
> > > > On Thu, Jan 19, 2023, Thinh Nguyen wrote:
> > > > > Hi,
> > > > >
> > > > > On Sun, Jan 15, 2023, Krishna Kurapati wrote:
> > > > > > Currently the DWC3 driver supports only single port controller
> > > > > > which requires at most one HS and one SS PHY.
> > > > >
> > > > > Add note here that multi-port is for host mode for clarity.
> > > > >
> > > > > >
> > > > > > But the DWC3 USB controller can be connected to multiple ports and
> > > > > > each port can have their own PHYs. Each port of the multiport
> > > > > > controller can either be HS+SS capable or HS only capable
> > > > > > Proper quantification of them is required to modify GUSB2PHYCFG
> > > > > > and GUSB3PIPECTL registers appropriately.
> > > > > >
> > > > > > Add support for detecting, obtaining and configuring phy's supported
> > > > > > by a multiport controller and limit the max number of ports
> > > > > > supported to 4.
> > > > > >
> > > > > > Signed-off-by: Harsh Agarwal <quic_harshq@xxxxxxxxxxx>
> > > > > > Signed-off-by: Krishna Kurapati <quic_kriskura@xxxxxxxxxxx>
> > > > > > ---
> > > > > > drivers/usb/dwc3/core.c | 304 +++++++++++++++++++++++++++++-----------
> > > > > > drivers/usb/dwc3/core.h | 15 +-
> > > > > > drivers/usb/dwc3/drd.c | 14 +-
> > > > > > 3 files changed, 244 insertions(+), 89 deletions(-)
> > > > > >
> > > > > > diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c
> > > > > > index 476b63618511..7e0a9a598dfd 100644
> > > > > > --- a/drivers/usb/dwc3/core.c
> > > > > > +++ b/drivers/usb/dwc3/core.c
> > > > > > @@ -120,7 +120,7 @@ static void __dwc3_set_mode(struct work_struct *work)
> > > > > > {
> > > > > > struct dwc3 *dwc = work_to_dwc(work);
> > > > > > unsigned long flags;
> > > > > > - int ret;
> > > > > > + int ret, i;
> > > > >
> > > > > Can we declare variables in separate lines here and other places.
> > > > >
> > > > > > u32 reg;
> > > > > > u32 desired_dr_role;
> > > > > > @@ -200,8 +200,10 @@ static void __dwc3_set_mode(struct work_struct *work)
> > > > > > } else {
> > > > > > if (dwc->usb2_phy)
> > > > > > otg_set_vbus(dwc->usb2_phy->otg, true);
> > > > > > - phy_set_mode(dwc->usb2_generic_phy, PHY_MODE_USB_HOST);
> > > > > > - phy_set_mode(dwc->usb3_generic_phy, PHY_MODE_USB_HOST);
> > > > > > + for (i = 0; i < dwc->num_ports; i++) {
> > > >
> > > > BTW, is num_ports the total of usb2 + usb3 ports?
> > > Hi Thinh,
> > >
> > > No, num_ports is just the total number of hw usb ports present (presuming
> > > each port is hs capable, this is just the number of HS Phy's available).
> > >
> >
> > I see, thanks. Can you also make this clear in its description. I got
> > mixed up at some point for the equivalent of HCPARAMS1.MAXPORTS.
> >
> > Thanks,
> > Thinh
>
> Sure, Will add this to commit text.
> But as you rightly mentioned, HCSPARAMS1 gives the total number of HS+SS
> Phy's available (HCSPARAMS1.MAXPORTS). Is there a way to segregate this
> value (to just number of hs and ss).
>
We need to walk through each port and check its capability, and we can
check the port's major/minor revision to determine whether it's SS
capable. See xhci driver's logic and how it calls xhci_add_in_port().
Thanks,
Thinh
