On Thu, Jan 19, 2023 at 04:26:58PM +0000, Sudip Mukherjee wrote: > On Mon, Jan 9, 2023 at 4:25 PM Serge Semin <fancer.lancer@xxxxxxxxx> wrote: > > > > Hello Sudip > > > > On Thu, Jan 05, 2023 at 01:20:39AM +0300, Serge Semin wrote: > > > Hi Sudip > > > > > > On Sun, Dec 18, 2022 at 08:45:26PM +0300, Serge Semin wrote: > > > > Hi Sudip > > > > > > > > On Mon, Dec 12, 2022 at 06:07:17PM +0000, Sudip Mukherjee wrote: > > > > > The is v2 of the patch series adding enhanced SPI support. Some Synopsys SSI > > > > > controllers support enhanced SPI which includes Dual mode, Quad mode and > > > > > Octal mode. DWC_ssi includes clock stretching feature in enhanced SPI modes > > > > > which can be used to prevent FIFO underflow and overflow conditions while > > > > > transmitting or receiving the data respectively. > > > > > > > > > > This is almost a complete rework based on the review from Serge. > > > > > > > > Thank you very much for the series. I'll have a look at it on the next > > > > week. > > > > > > Just so you know. I haven't forgot about the series. There are some > > > problematic parts which I need to give more thinking than I originally > > > expected. I'll submit my comments very soon. Sorry for the delay. > > > > > > Good news is that I've got the HW-manual for the DW SSI v1.01a > > > IP-core. So I'll no longer need to ask of you about that device > > > implementation specifics. > > > > Finally I managed to consolidate my thoughts regarding your patchset. > > Here is the summary. Some specific comments will be sent in-reply to > > the corresponding patches. > > > > First of all there is a crucial difference between eSPI capability > > available on DW APB SSI and DW AHB SSI controllers: > > DW APB SSI 4.x: > > + Tx until FIFO is empty > > + No clock stretching at all > > Thanks for your detailed review and all the additional details about > DW APB SSI. I did not have this datasheet to check. > So, that will mean I can remove the APB versiom detection from my next series. > But unfortunately, I don't have access to the hardware currently to > prepare and test the v3 series. It will be delayed a bit and I am > hoping I will be able to work on this by early March. Ok. Thanks for the update. Whenever you're ready I'll be here for review. -Serge(y) > > > -- > Regards > Sudip
