On Thu, Jan 12, 2023 at 11:15:57PM +0200, Dmitry Baryshkov wrote:
> On 12/01/2023 22:44, Melody Olvera wrote:
> > From: Taniya Das <quic_tdas@xxxxxxxxxxx>
> >
> > Add Global Clock Controller (GCC) support for QDU1000 and QRU1000 SoCs.
> >
> > Signed-off-by: Taniya Das <quic_tdas@xxxxxxxxxxx>
> > Signed-off-by: Melody Olvera <quic_molvera@xxxxxxxxxxx>
> > Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> > ---
> > drivers/clk/qcom/Kconfig | 8 +
> > drivers/clk/qcom/Makefile | 1 +
> > drivers/clk/qcom/gcc-qdu1000.c | 2653 ++++++++++++++++++++++++++++++++
> > 3 files changed, 2662 insertions(+)
> > create mode 100644 drivers/clk/qcom/gcc-qdu1000.c
> >
>
> [skipped the rest]
>
> > +};
> > +
> > +static struct clk_regmap_mux gcc_pcie_0_pipe_clk_src = {
> > + .reg = 0x9d064,
> > + .shift = 0,
> > + .width = 2,
> > + .parent_map = gcc_parent_map_7,
> > + .clkr = {
> > + .hw.init = &(const struct clk_init_data) {
> > + .name = "gcc_pcie_0_pipe_clk_src",
> > + .parent_data = gcc_parent_data_7,
> > + .num_parents = ARRAY_SIZE(gcc_parent_data_7),
> > + .ops = &clk_regmap_mux_closest_ops,
>
> I think this should use clk_regmap_phy_mux_ops.
>
I believe so too. So I updated this as I applied the patch.
@Melody, please send a fix if bringing up PCIe shows this to be wrong.
Thanks,
Bjorn
> > + },
> > + },
> > +};
> > +--
> With best wishes
> Dmitry
>
