From: Liu Ying <victor.liu@xxxxxxx>
This patch adds pwm_lvds0/1 support together with a
i.MX 8QM LVDS subsystem device tree.
Signed-off-by: Liu Ying <victor.liu@xxxxxxx>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@xxxxxxxxxxx>
---
Changes in v4:
- New patch combining the following downstream patches limitted to LVDS
PWM functionality for now:
commit 036c6b28a186 ("arm64: imx8qm.dtsi: Add LVDS0/1 subsystems support")
commit c3d29611d9d4 ("arm64: imx8qm-ss-lvds.dtsi: Add pwm_lvds0/1 support")
commit baf1b0f22f8a ("LF-882-1 arm64: imx8qm-ss-lvds.dtsi: Separate ipg clock for lvds0/1 subsystems")
.../boot/dts/freescale/imx8qm-ss-lvds.dtsi | 83 +++++++++++++++++++
arch/arm64/boot/dts/freescale/imx8qm.dtsi | 1 +
2 files changed, 84 insertions(+)
create mode 100644 arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
diff --git a/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
new file mode 100644
index 000000000000..4b940fc3c890
--- /dev/null
+++ b/arch/arm64/boot/dts/freescale/imx8qm-ss-lvds.dtsi
@@ -0,0 +1,83 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2023 NXP
+ */
+
+/ {
+ lvds1_subsys: bus@56240000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x56240000 0x0 0x56240000 0x10000>;
+
+ lvds0_ipg_clk: clock-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "lvds0_ipg_clk";
+ };
+
+ lvds0_pwm_lpcg: clock-controller@5624300c {
+ compatible = "fsl,imx8qm-lpcg";
+ reg = <0x5624300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds0_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds0_pwm_lpcg_clk",
+ "lvds0_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ };
+
+ pwm_lvds0: pwm@56244000 {
+ compatible = "fsl,imx27-pwm";
+ reg = <0x56244000 0x1000>;
+ clocks = <&lvds0_pwm_lpcg 0>,
+ <&lvds0_pwm_lpcg 1>;
+ clock-names = "per", "ipg";
+ assigned-clocks = <&clk IMX_SC_R_LVDS_0_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <2>;
+ power-domains = <&pd IMX_SC_R_LVDS_0_PWM_0>;
+ status = "disabled";
+ };
+ };
+
+ lvds2_subsys: bus@57240000 {
+ compatible = "simple-bus";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0x57240000 0x0 0x57240000 0x10000>;
+
+ lvds1_ipg_clk: clock-lvds-ipg {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <24000000>;
+ clock-output-names = "lvds1_ipg_clk";
+ };
+
+ lvds1_pwm_lpcg: clock-controller@5724300c {
+ compatible = "fsl,imx8qm-lpcg";
+ reg = <0x5724300c 0x4>;
+ #clock-cells = <1>;
+ clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>,
+ <&lvds1_ipg_clk>;
+ clock-indices = <IMX_LPCG_CLK_0>, <IMX_LPCG_CLK_4>;
+ clock-output-names = "lvds1_pwm_lpcg_clk",
+ "lvds1_pwm_lpcg_ipg_clk";
+ power-domains = <&pd IMX_SC_R_LVDS_1_PWM_0>;
+ };
+
+ pwm_lvds1: pwm@57244000 {
+ compatible = "fsl,imx27-pwm";
+ reg = <0x57244000 0x1000>;
+ clock-names = "ipg", "per";
+ clocks = <&lvds1_pwm_lpcg 4>,
+ <&lvds1_pwm_lpcg 1>;
+ assigned-clocks = <&clk IMX_SC_R_LVDS_1_PWM_0 IMX_SC_PM_CLK_PER>;
+ assigned-clock-rates = <24000000>;
+ #pwm-cells = <2>;
+ status = "disabled";
+ };
+ };
+};
diff --git a/arch/arm64/boot/dts/freescale/imx8qm.dtsi b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
index 41ce8336f29e..422edd2f20fa 100644
--- a/arch/arm64/boot/dts/freescale/imx8qm.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8qm.dtsi
@@ -222,3 +222,4 @@ rtc: rtc {
#include "imx8qm-ss-dma.dtsi"
#include "imx8qm-ss-conn.dtsi"
#include "imx8qm-ss-lsio.dtsi"
+#include "imx8qm-ss-lvds.dtsi"
--
2.35.1
