On 17/01/2023 14:45, Geert Uytterhoeven wrote:
> Hi Siddharth,
>
> On Wed, Jan 4, 2023 at 11:37 AM Siddharth Vadapalli <s-vadapalli@xxxxxx> wrote:
>> Update bindings for TI K3 J721e SoC which contains 9 ports (8 external
>> ports) CPSW9G module and add compatible for it.
>>
>> Changes made:
>> - Add new compatible ti,j721e-cpswxg-nuss for CPSW9G.
>> - Extend pattern properties for new compatible.
>> - Change maximum number of CPSW ports to 8 for new compatible.
>>
>> Signed-off-by: Siddharth Vadapalli <s-vadapalli@xxxxxx>
>> Reviewed-by: Rob Herring <robh@xxxxxxxxxx>
>
> Thanks for your patch, which is now commit c85b53e32c8ecfe6
> ("dt-bindings: net: ti: k3-am654-cpsw-nuss: Add J721e CPSW9G
> support") in net-next.
>
> You forgot to document the presence of the new optional
> "serdes-phy" PHY.
I think we should start rejecting most of bindings without DTS, because
submitters really like to forget to make complete bindings. Having a DTS
with such undocumented property gives a bit bigger chance it will get an
attention. :(
Best regards,
Krzysztof
