On 16/01/23 21:43, Doug Brown wrote:
> Add ability to have an optional core clock just like the pxav3 driver.
> The PXA168 needs this because its SDHC controllers have separate core
> and io clocks that both need to be enabled. This also correctly matches
> the documented devicetree bindings for this driver.
>
> Reported-by: kernel test robot <lkp@xxxxxxxxx>
> Reported-by: Dan Carpenter <error27@xxxxxxxxx>
> Signed-off-by: Doug Brown <doug@xxxxxxxxxxxxx>
Acked-by: Adrian Hunter <adrian.hunter@xxxxxxxxx>
> ---
> The Reported-by tags above refer to a missing assignment to ret in an
> earlier version of this patch. The kernel test robot caught it.
>
> drivers/mmc/host/sdhci-pxav2.c | 9 ++++++++-
> 1 file changed, 8 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/mmc/host/sdhci-pxav2.c b/drivers/mmc/host/sdhci-pxav2.c
> index f5c86e1ba734..3141901e1558 100644
> --- a/drivers/mmc/host/sdhci-pxav2.c
> +++ b/drivers/mmc/host/sdhci-pxav2.c
> @@ -191,7 +191,7 @@ static int sdhci_pxav2_probe(struct platform_device *pdev)
> const struct sdhci_pxa_variant *variant;
>
> int ret;
> - struct clk *clk;
> + struct clk *clk, *clk_core;
>
> host = sdhci_pltfm_init(pdev, NULL, 0);
> if (IS_ERR(host))
> @@ -214,6 +214,13 @@ static int sdhci_pxav2_probe(struct platform_device *pdev)
> goto free;
> }
>
> + clk_core = devm_clk_get_optional_enabled(dev, "core");
> + if (IS_ERR(clk_core)) {
> + ret = PTR_ERR(clk_core);
> + dev_err_probe(dev, ret, "failed to enable core clock\n");
> + goto disable_clk;
> + }
> +
> host->quirks = SDHCI_QUIRK_BROKEN_ADMA
> | SDHCI_QUIRK_BROKEN_TIMEOUT_VAL
> | SDHCI_QUIRK_CAP_CLOCK_BASE_BROKEN;
