On this board the PHY is the ref clock provider. So, configure ethernet
reference clock as input.
Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx>
---
arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts | 13 ++++++++-----
1 file changed, 8 insertions(+), 5 deletions(-)
diff --git a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
index 864dc5018451..33825b5a8f26 100644
--- a/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
+++ b/arch/arm/boot/dts/imx6dl-eckelmann-ci4x10.dts
@@ -28,6 +28,7 @@ rmii_clk: clock-rmii {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <50000000>;
+ clock-output-names = "enet_ref_pad";
};
reg_usb_h1_vbus: regulator-usb-h1-vbus {
@@ -64,6 +65,13 @@ &can2 {
status = "okay";
};
+&clks {
+ clocks = <&rmii_clk>;
+ clock-names = "enet_ref_pad";
+ assigned-clocks = <&clks IMX6QDL_CLK_ENET_REF_SEL>;
+ assigned-clock-parents = <&rmii_clk>;
+};
+
&ecspi2 {
pinctrl-names = "default";
pinctrl-0 = <&pinctrl_ecspi2>;
@@ -297,11 +305,6 @@ &fec {
phy-mode = "rmii";
phy-reset-gpios = <&gpio1 18 GPIO_ACTIVE_LOW>;
phy-handle = <&phy>;
- clocks = <&clks IMX6QDL_CLK_ENET>,
- <&clks IMX6QDL_CLK_ENET>,
- <&rmii_clk>,
- <&clks IMX6QDL_CLK_ENET_REF>;
- clock-names = "ipg", "ahb", "ptp", "enet_out";
status = "okay";
mdio {
--
2.30.2
