Add dtsi nodes related to coresight debug units such as cti, etm, etr, funnel(s), replicator(s), etc. for Qualcomm sm6115 SoC. Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx> --- - Changes since v1: - v1 can be viewed here: https://lore.kernel.org/linux-arm-msm/20230114210754.353912-1-bhupesh.sharma@xxxxxxxxxx/ - Addressed stm node ordering as per Konrad's review on v1. - Collected Konrad's R-B. arch/arm64/boot/dts/qcom/sm6115.dtsi | 612 +++++++++++++++++++++++++++ 1 file changed, 612 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 478c5d009272..08f93b1dc2f8 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -1237,6 +1237,618 @@ dispcc: clock-controller@5f00000 { #power-domain-cells = <1>; }; + stm@8002000 { + compatible = "arm,coresight-stm", "arm,primecell"; + reg = <0x08002000 0x1000>, + <0x0e280000 0x180000>; + reg-names = "stm-base", "stm-stimulus-base"; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + stm_out: endpoint { + remote-endpoint = <&funnel_in0_in>; + }; + }; + }; + }; + + cti0: cti@8010000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08010000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti1: cti@8011000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08011000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti2: cti@8012000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08012000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti3: cti@8013000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08013000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti4: cti@8014000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08014000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti5: cti@8015000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08015000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti6: cti@8016000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08016000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti7: cti@8017000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08017000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti8: cti@8018000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08018000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti9: cti@8019000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x08019000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti10: cti@801a000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801a000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti11: cti@801b000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801b000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti12: cti@801c000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801c000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti13: cti@801d000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801d000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti14: cti@801e000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801e000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + cti15: cti@801f000 { + compatible = "arm,coresight-cti", "arm,primecell"; + reg = <0x0801f000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + }; + + replicator@8046000 { + compatible = "arm,coresight-dynamic-replicator", "arm,primecell"; + reg = <0x08046000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + replicator_out: endpoint { + remote-endpoint = <&etr_in>; + }; + }; + }; + + in-ports { + port { + replicator_in: endpoint { + remote-endpoint = <&etf_out>; + }; + }; + }; + }; + + etf@8047000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x08047000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + in-ports { + port { + etf_in: endpoint { + remote-endpoint = <&merge_funnel_out>; + }; + }; + }; + + out-ports { + port { + etf_out: endpoint { + remote-endpoint = <&replicator_in>; + }; + }; + }; + }; + + etr@8048000 { + compatible = "arm,coresight-tmc", "arm,primecell"; + reg = <0x08048000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + in-ports { + port { + etr_in: endpoint { + remote-endpoint = <&replicator_out>; + }; + }; + }; + }; + + funnel@8041000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x08041000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_in0_out: endpoint { + remote-endpoint = <&merge_funnel_in0>; + }; + }; + }; + + in-ports { + port { + funnel_in0_in: endpoint { + remote-endpoint = <&stm_out>; + }; + }; + }; + }; + + funnel@8042000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x08042000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_in1_out: endpoint { + remote-endpoint = <&merge_funnel_in1>; + }; + }; + }; + + in-ports { + port { + funnel_in1_in: endpoint { + remote-endpoint = <&funnel_apss1_out>; + }; + }; + }; + }; + + funnel@8045000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x08045000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + merge_funnel_out: endpoint { + remote-endpoint = <&etf_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + merge_funnel_in0: endpoint { + remote-endpoint = <&funnel_in0_out>; + }; + }; + + port@1 { + reg = <1>; + merge_funnel_in1: endpoint { + remote-endpoint = <&funnel_in1_out>; + }; + }; + }; + }; + + etm@9040000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09040000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU0>; + + status = "disabled"; + + out-ports { + port { + etm0_out: endpoint { + remote-endpoint = <&funnel_apss0_in0>; + }; + }; + }; + }; + + etm@9140000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09140000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU1>; + + status = "disabled"; + + out-ports { + port { + etm1_out: endpoint { + remote-endpoint = <&funnel_apss0_in1>; + }; + }; + }; + }; + + etm@9240000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09240000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU2>; + + status = "disabled"; + + out-ports { + port { + etm2_out: endpoint { + remote-endpoint = <&funnel_apss0_in2>; + }; + }; + }; + }; + + etm@9340000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09340000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU3>; + + status = "disabled"; + + out-ports { + port { + etm3_out: endpoint { + remote-endpoint = <&funnel_apss0_in3>; + }; + }; + }; + }; + + etm@9440000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09440000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU4>; + + status = "disabled"; + + out-ports { + port { + etm4_out: endpoint { + remote-endpoint = <&funnel_apss0_in4>; + }; + }; + }; + }; + + etm@9540000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09540000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU5>; + + status = "disabled"; + + out-ports { + port { + etm5_out: endpoint { + remote-endpoint = <&funnel_apss0_in5>; + }; + }; + }; + }; + + etm@9640000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09640000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU6>; + + status = "disabled"; + + out-ports { + port { + etm6_out: endpoint { + remote-endpoint = <&funnel_apss0_in6>; + }; + }; + }; + }; + + etm@9740000 { + compatible = "arm,coresight-etm4x", "arm,primecell"; + reg = <0x09740000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + arm,coresight-loses-context-with-cpu; + + cpu = <&CPU7>; + + status = "disabled"; + + out-ports { + port { + etm7_out: endpoint { + remote-endpoint = <&funnel_apss0_in7>; + }; + }; + }; + }; + + funnel@9800000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x09800000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_apss0_out: endpoint { + remote-endpoint = <&funnel_apss1_in>; + }; + }; + }; + + in-ports { + #address-cells = <1>; + #size-cells = <0>; + + port@0 { + reg = <0>; + funnel_apss0_in0: endpoint { + remote-endpoint = <&etm0_out>; + }; + }; + + port@1 { + reg = <1>; + funnel_apss0_in1: endpoint { + remote-endpoint = <&etm1_out>; + }; + }; + + port@2 { + reg = <2>; + funnel_apss0_in2: endpoint { + remote-endpoint = <&etm2_out>; + }; + }; + + port@3 { + reg = <3>; + funnel_apss0_in3: endpoint { + remote-endpoint = <&etm3_out>; + }; + }; + + port@4 { + reg = <4>; + funnel_apss0_in4: endpoint { + remote-endpoint = <&etm4_out>; + }; + }; + + port@5 { + reg = <5>; + funnel_apss0_in5: endpoint { + remote-endpoint = <&etm5_out>; + }; + }; + + port@6 { + reg = <6>; + funnel_apss0_in6: endpoint { + remote-endpoint = <&etm6_out>; + }; + }; + + port@7 { + reg = <7>; + funnel_apss0_in7: endpoint { + remote-endpoint = <&etm7_out>; + }; + }; + }; + }; + + funnel@9810000 { + compatible = "arm,coresight-dynamic-funnel", "arm,primecell"; + reg = <0x09810000 0x1000>; + + clocks = <&rpmcc RPM_SMD_QDSS_CLK>; + clock-names = "apb_pclk"; + + status = "disabled"; + + out-ports { + port { + funnel_apss1_out: endpoint { + remote-endpoint = <&funnel_in1_in>; + }; + }; + }; + + in-ports { + port { + funnel_apss1_in: endpoint { + remote-endpoint = <&funnel_apss0_out>; + }; + }; + }; + }; + apps_smmu: iommu@c600000 { compatible = "qcom,sm6115-smmu-500", "qcom,smmu-500", "arm,mmu-500"; reg = <0x0c600000 0x80000>; -- 2.38.1
