Convert the bindings of the Freescale Pixel Pipeline to YAML. The conversion drops the previously listed compatibles for several SoCs. It is unclear, if the PXP on these SoCs is compatible to any of the PXPs on the existing SoCs and would allow to reuse the already defined compatibles. The missing compatibles should be brought back when the support for the PXP on these SoCs is added. Reviewed-by: Laurent Pinchart <laurent.pinchart@xxxxxxxxxxxxxxxx> Reviewed-by: Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> Signed-off-by: Michael Tretter <m.tretter@xxxxxxxxxxxxxx> --- Changelog: v2: - add fsl,imx6sll-pxp and fsl,imx6sx-pxp compatibles - restrict number of interrupts per variant - cleanup syntax v2.1: - use enum for compatibles - add power-domains property - fix syntax for specifying the required number of interrupts - fix number of interrupts for fsl,imx6ul-pxp --- .../bindings/media/fsl,imx6ull-pxp.yaml | 88 +++++++++++++++++++ .../devicetree/bindings/media/fsl-pxp.txt | 26 ------ 2 files changed, 88 insertions(+), 26 deletions(-) create mode 100644 Documentation/devicetree/bindings/media/fsl,imx6ull-pxp.yaml delete mode 100644 Documentation/devicetree/bindings/media/fsl-pxp.txt diff --git a/Documentation/devicetree/bindings/media/fsl,imx6ull-pxp.yaml b/Documentation/devicetree/bindings/media/fsl,imx6ull-pxp.yaml new file mode 100644 index 000000000000..84a5e894ace4 --- /dev/null +++ b/Documentation/devicetree/bindings/media/fsl,imx6ull-pxp.yaml @@ -0,0 +1,88 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/media/fsl,imx6ull-pxp.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Freescale Pixel Pipeline + +maintainers: + - Philipp Zabel <p.zabel@xxxxxxxxxxxxxx> + - Michael Tretter <m.tretter@xxxxxxxxxxxxxx> + +description: + The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine + that supports scaling, colorspace conversion, alpha blending, rotation, and + pixel conversion via lookup table. Different versions are present on various + i.MX SoCs from i.MX23 to i.MX7. + +properties: + compatible: + oneOf: + - enum: + - fsl,imx6ul-pxp + - fsl,imx6ull-pxp + - fsl,imx7d-pxp + - items: + - enum: + - fsl,imx6sll-pxp + - fsl,imx6sx-pxp + - const: fsl,imx6ull-pxp + + reg: + maxItems: 1 + + interrupts: + minItems: 1 + maxItems: 2 + + clocks: + maxItems: 1 + + clock-names: + const: axi + + power-domains: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + +allOf: + - if: + properties: + compatible: + contains: + enum: + - fsl,imx6sx-pxp + - fsl,imx6ul-pxp + then: + properties: + interrupts: + maxItems: 1 + else: + properties: + interrupts: + minItems: 2 + maxItems: 2 + +additionalProperties: false + +examples: + - | + #include <dt-bindings/clock/imx6ul-clock.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + + pxp: pxp@21cc000 { + compatible = "fsl,imx6ull-pxp"; + reg = <0x021cc000 0x4000>; + interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "axi"; + clocks = <&clks IMX6UL_CLK_PXP>; + }; diff --git a/Documentation/devicetree/bindings/media/fsl-pxp.txt b/Documentation/devicetree/bindings/media/fsl-pxp.txt deleted file mode 100644 index f8090e06530d..000000000000 --- a/Documentation/devicetree/bindings/media/fsl-pxp.txt +++ /dev/null @@ -1,26 +0,0 @@ -Freescale Pixel Pipeline -======================== - -The Pixel Pipeline (PXP) is a memory-to-memory graphics processing engine -that supports scaling, colorspace conversion, alpha blending, rotation, and -pixel conversion via lookup table. Different versions are present on various -i.MX SoCs from i.MX23 to i.MX7. - -Required properties: -- compatible: should be "fsl,<soc>-pxp", where SoC can be one of imx23, imx28, - imx6dl, imx6sl, imx6sll, imx6ul, imx6sx, imx6ull, or imx7d. -- reg: the register base and size for the device registers -- interrupts: the PXP interrupt, two interrupts for imx6ull and imx7d. -- clock-names: should be "axi" -- clocks: the PXP AXI clock - -Example: - -pxp@21cc000 { - compatible = "fsl,imx6ull-pxp"; - reg = <0x021cc000 0x4000>; - interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>, - <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "axi"; - clocks = <&clks IMX6UL_CLK_PXP>; -}; -- 2.30.2
