On Fri, 13 Jan 2023, Oleksij Rempel wrote: > Add ethernet refclock mux support and set it to internal clock by > default. This configuration will not affect existing boards. > > clock tree before this patch: > fec1 <- enet1_ref_125m (gate) <- enet1_ref (divider) <-, > |- pll6_enet > fec2 <- enet2_ref_125m (gate) <- enet2_ref (divider) <-´ > > after this patch: > fec1 <- enet1_ref_sel(mux) <- enet1_ref_125m (gate) <- ... > `--<> enet1_ref_pad |- pll6_enet > fec2 <- enet2_ref_sel(mux) <- enet2_ref_125m (gate) <- ... > `--<> enet2_ref_pad > > Signed-off-by: Oleksij Rempel <o.rempel@xxxxxxxxxxxxxx> > --- > drivers/clk/imx/clk-imx6ul.c | 26 +++++++++++++++++++++ > include/dt-bindings/clock/imx6ul-clock.h | 6 ++++- > include/linux/mfd/syscon/imx6q-iomuxc-gpr.h | 6 +++-- > 3 files changed, 35 insertions(+), 3 deletions(-) [...] > --- a/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > +++ b/include/linux/mfd/syscon/imx6q-iomuxc-gpr.h > @@ -451,8 +451,10 @@ > #define IMX6SX_GPR12_PCIE_RX_EQ_2 (0x2 << 0) > > /* For imx6ul iomux gpr register field define */ > -#define IMX6UL_GPR1_ENET1_CLK_DIR (0x1 << 17) > -#define IMX6UL_GPR1_ENET2_CLK_DIR (0x1 << 18) > +#define IMX6UL_GPR1_ENET2_TX_CLK_DIR BIT(18) > +#define IMX6UL_GPR1_ENET1_TX_CLK_DIR BIT(17) > +#define IMX6UL_GPR1_ENET2_CLK_SEL BIT(14) > +#define IMX6UL_GPR1_ENET1_CLK_SEL BIT(13) > #define IMX6UL_GPR1_ENET1_CLK_OUTPUT (0x1 << 17) > #define IMX6UL_GPR1_ENET2_CLK_OUTPUT (0x1 << 18) > #define IMX6UL_GPR1_ENET_CLK_DIR (0x3 << 17) Why not convert more of them them? Either way, could you please refrain from sending me subsequent patch-sets please. Acked-by: Lee Jones <lee@xxxxxxxxxx> -- Lee Jones [李琼斯]
