On Thu, Jan 12, 2023 at 03:59:25PM +0200, Abel Vesa wrote:
> Add UFS host controller and PHY nodes.
>
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> ---
>
> Changes since v1:
> * dropped ufs_mem_phy_lanes child node, like Johan suggested
> * addressed Konrad comments.
>
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 78 ++++++++++++++++++++++++++--
> 1 file changed, 75 insertions(+), 3 deletions(-)
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> index 59756ec11564..d20b5fbcb2c3 100644
> --- a/arch/arm64/boot/dts/qcom/sm8550.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -649,9 +649,9 @@ gcc: clock-controller@100000 {
> <0>,
> <0>,
> <0>,
> - <0>,
> - <0>,
> - <0>,
> + <&ufs_mem_phy 0>,
> + <&ufs_mem_phy 1>,
> + <&ufs_mem_phy 2>,
> <0>;
> };
>
> @@ -1571,6 +1571,78 @@ crypto: crypto@1de0000 {
> interconnect-names = "memory";
> };
>
> + ufs_mem_phy: phy@1d80000 {
> + compatible = "qcom,sm8550-qmp-ufs-phy";
> + reg = <0x0 0x01d80000 0x0 0x2000>;
> + clock-names = "ref", "qref";
> + clocks = <&gcc GCC_UFS_PHY_PHY_AUX_CLK>,
> + <&tcsr TCSR_UFS_CLKREF_EN>;
> +
> + power-domains = <&gcc UFS_MEM_PHY_GDSC>;
> +
> + resets = <&ufs_mem_hc 0>;
> + reset-names = "ufsphy";
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + #phy-cells = <0>;
> +
> + #clock-cells = <1>;
> +
> + ranges;
Isn't this a leftover from the older binding?
> +
> + status = "disabled";
> + };
> +
> + ufs_mem_hc: ufshc@1d84000 {
ufs@ I believe.
> + compatible = "qcom,sm8550-ufshc", "qcom,ufshc",
> + "jedec,ufs-2.0";
> + reg = <0x0 0x01d84000 0x0 0x3000>;
> + interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH>;
> + phys = <&ufs_mem_phy>;
> + phy-names = "ufsphy";
> + lanes-per-direction = <2>;
> + #reset-cells = <1>;
> + resets = <&gcc GCC_UFS_PHY_BCR>;
> + reset-names = "rst";
> +
> + power-domains = <&gcc UFS_PHY_GDSC>;
> +
> + iommus = <&apps_smmu 0x60 0x0>;
> +
> + interconnects = <&aggre1_noc MASTER_UFS_MEM 0 &mc_virt SLAVE_EBI1 0>,
> + <&gem_noc MASTER_APPSS_PROC 0 &config_noc SLAVE_UFS_MEM_CFG 0>;
> +
> + interconnect-names = "ufs-ddr", "cpu-ufs";
> + clock-names = "core_clk",
> + "bus_aggr_clk",
> + "iface_clk",
> + "core_clk_unipro",
> + "ref_clk",
> + "tx_lane0_sync_clk",
> + "rx_lane0_sync_clk",
> + "rx_lane1_sync_clk";
> + clocks = <&gcc GCC_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_AGGRE_UFS_PHY_AXI_CLK>,
> + <&gcc GCC_UFS_PHY_AHB_CLK>,
> + <&gcc GCC_UFS_PHY_UNIPRO_CORE_CLK>,
> + <&rpmhcc RPMH_LN_BB_CLK3>,
ref_clk here represents the refclk to the memory device, which I believe
is what is the thing you have as <&tcsrcc TCSR_UFS_PAD_CLKREF_EN>.
> + <&gcc GCC_UFS_PHY_TX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_0_CLK>,
> + <&gcc GCC_UFS_PHY_RX_SYMBOL_1_CLK>;
> + freq-table-hz =
> + <75000000 300000000>,
GCC_UFS_PHY_AXI_CLK requires SM8550_CX (UFS_PHY_GDSC) to be voted to
nominal, so please ensure that this is done. (e.g. using required-opps)
Thanks,
Bjorn
> + <0 0>,
> + <0 0>,
> + <75000000 300000000>,
> + <100000000 403000000>,
> + <0 0>,
> + <0 0>,
> + <0 0>;
> + status = "disabled";
> + };
> +
> tcsr_mutex: hwlock@1f40000 {
> compatible = "qcom,tcsr-mutex";
> reg = <0 0x01f40000 0 0x20000>;
> --
> 2.34.1
>
