On 08.12.2022 13:52, Claudiu Beznea wrote:
> The 2nd DDR clock for sam9x60 DDR controller is peripheral clock with
> id 49.
>
> Fixes: 1e5f532c2737 ("ARM: dts: at91: sam9x60: add device tree for soc and board")
> Signed-off-by: Claudiu Beznea <claudiu.beznea@xxxxxxxxxxxxx>
Applied to at91-fixes, thanks!
> ---
> arch/arm/boot/dts/sam9x60.dtsi | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/sam9x60.dtsi b/arch/arm/boot/dts/sam9x60.dtsi
> index 8f5477e307dd..37a5d96aaf64 100644
> --- a/arch/arm/boot/dts/sam9x60.dtsi
> +++ b/arch/arm/boot/dts/sam9x60.dtsi
> @@ -564,7 +564,7 @@ pmecc: ecc-engine@ffffe000 {
> mpddrc: mpddrc@ffffe800 {
> compatible = "microchip,sam9x60-ddramc", "atmel,sama5d3-ddramc";
> reg = <0xffffe800 0x200>;
> - clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_CORE PMC_MCK>;
> + clocks = <&pmc PMC_TYPE_SYSTEM 2>, <&pmc PMC_TYPE_PERIPHERAL 49>;
> clock-names = "ddrck", "mpddr";
> };
>
