On 11.01.2023 22:51, Dmitry Baryshkov wrote:
> On 11/01/2023 22:58, Konrad Dybcio wrote:
>>
>>
>> On 11.01.2023 20:19, Dmitry Baryshkov wrote:
>>> Change PLL programming to let both power and performance cluster clocks
>>> to start from the maximum common frequency.
>>>
>>> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
>>> ---
>> Can you point me to the source of this? My local random msm-3.18 has this at 60.
>
> Yes, but with 60 cluster start at the unlisted frequency (60 * 19.2 = 1152 MHz), which leads to cpufreq whining and immediately performing a switch.
>
> I modified this to 54 * 19.2 = 1036.8 MHz which is supported by both power and performance clusters. Maybe we could have gone to 58 * 19.2 = 1113. Mhz or to 62 * 19.2 = 1190.4 MHz, but as all the safety and power measures and not probed at this point, I preferred to rather be safe than sorry.
Okay, please include this reasoning in the commit message, as nobody
would guess it fixes this issue..
Konrad
>
>>
>> Konrad
>>> drivers/clk/qcom/clk-cpu-8996.c | 2 +-
>>> 1 file changed, 1 insertion(+), 1 deletion(-)
>>>
>>> diff --git a/drivers/clk/qcom/clk-cpu-8996.c b/drivers/clk/qcom/clk-cpu-8996.c
>>> index ed8cb558e1aa..d51965fda56d 100644
>>> --- a/drivers/clk/qcom/clk-cpu-8996.c
>>> +++ b/drivers/clk/qcom/clk-cpu-8996.c
>>> @@ -102,7 +102,7 @@ static const u8 alt_pll_regs[PLL_OFF_MAX_REGS] = {
>>> /* PLLs */
>>> static const struct alpha_pll_config hfpll_config = {
>>> - .l = 60,
>>> + .l = 54,
>>> .config_ctl_val = 0x200d4828,
>>> .config_ctl_hi_val = 0x006,
>>> .test_ctl_val = 0x1c000000,
>
