Hi,
On Wed, Jan 11, 2023 at 8:37 PM Allen-KH Cheng
<allen-kh.cheng@xxxxxxxxxxxx> wrote:
>
> Add display nodes and GCE info for MT8186 SoC. Also, add GCE
> (Global Command Engine) properties to the display nodes in order to
> enable the usage of the CMDQ (Command Queue), which is required for
> operating the display.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@xxxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/mediatek/mt8186.dtsi | 128 +++++++++++++++++++++++
> 1 file changed, 128 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> index eab30ab01572..8670d37970ef 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
> @@ -5,6 +5,7 @@
> */
> /dts-v1/;
> #include <dt-bindings/clock/mt8186-clk.h>
> +#include <dt-bindings/gce/mt8186-gce.h>
> #include <dt-bindings/interrupt-controller/arm-gic.h>
> #include <dt-bindings/interrupt-controller/irq.h>
> #include <dt-bindings/memory/mt8186-memory-port.h>
> @@ -632,6 +633,15 @@
> clocks = <&clk13m>;
> };
>
> + gce: mailbox@1022c000 {
> + compatible = "mediatek,mt8186-gce";
> + reg = <0 0X1022c000 0 0x4000>;
> + interrupts = <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH 0>;
> + #mbox-cells = <2>;
> + clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
> + clock-names = "gce";
> + };
> +
> scp: scp@10500000 {
> compatible = "mediatek,mt8186-scp";
> reg = <0 0x10500000 0 0x40000>,
> @@ -1197,6 +1207,20 @@
> reg = <0 0x14000000 0 0x1000>;
> #clock-cells = <1>;
> #reset-cells = <1>;
> + mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
> + <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
> + };
> +
> + mutex: mutex@14001000 {
> + compatible = "mediatek,mt8186-disp-mutex";
> + reg = <0 0x14001000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_DISP_MUTEX0>;
> + interrupts = <GIC_SPI 295 IRQ_TYPE_LEVEL_HIGH 0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1401XXXX 0x1000 0x1000>;
> + mediatek,gce-events = <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_0>,
> + <CMDQ_EVENT_DISP_STREAM_DONE_ENG_EVENT_1>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> };
>
> smi_common: smi@14002000 {
> @@ -1230,6 +1254,49 @@
> power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> };
>
> + ovl0: ovl@14005000 {
If there's only one instance, you could drop the trailing zero. Same
for all the other nodes.
> + compatible = "mediatek,mt8186-disp-ovl",
> + "mediatek,mt8192-disp-ovl";
> + reg = <0 0x14005000 0 0x1000>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0>;
> + interrupts = <GIC_SPI 297 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu_mm IOMMU_PORT_L0_OVL_RDMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x5000 0x1000>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> + };
> +
> + ovl0_2l: ovl@14006000 {
I think this should be "ovl_2l0" or "ovl_2l" instead?
> + compatible = "mediatek,mt8186-disp-ovl-2l",
> + "mediatek,mt8192-disp-ovl-2l";
> + reg = <0 0x14006000 0 0x1000>;
> + power-domains = <&spm MT8186_POWER_DOMAIN_DIS>;
> + clocks = <&mmsys CLK_MM_DISP_OVL0_2L>;
> + interrupts = <GIC_SPI 298 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu_mm IOMMU_PORT_L1_OVL_2L_RDMA0>;
> + mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0x6000 0x1000>;
> + };
Also, this patch is missing the aliases for ovl* and rdma*. Without them
the display driver doesn't properly detect the second pipeline, and only
one CRTC is generated.
ChenYu
