On 10.01.2023 18:56, Konrad Dybcio wrote: > From: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx> > > Add the bindings for the CPR3 driver to the documentation. > > Reviewed-by: Rob Herring <robh@xxxxxxxxxx> > Signed-off-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxxx> > [Konrad: Add type reference to acc-syscon; update AGdR's email] > Signed-off-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx> > --- Need to add qcom,opp-oloop-vadj qcom,opp-cloop-vadj in next revision. Konrad > .../bindings/soc/qcom/qcom,cpr3.yaml | 242 ++++++++++++++++++ > 1 file changed, 242 insertions(+) > create mode 100644 Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > > diff --git a/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > new file mode 100644 > index 000000000000..52e87061a04b > --- /dev/null > +++ b/Documentation/devicetree/bindings/soc/qcom/qcom,cpr3.yaml > @@ -0,0 +1,242 @@ > +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: "http://devicetree.org/schemas/soc/qcom/qcom,cpr3.yaml#"; > +$schema: "http://devicetree.org/meta-schemas/core.yaml#"; > + > +title: Qualcomm Core Power Reduction v3/v4/Hardened (CPR3, CPR4, CPRh) > + > +description: | > + CPR (Core Power Reduction) is a technology to reduce core power on a CPU > + or other device. Each OPP of a device corresponds to a "corner" that has > + a range of valid voltages for a particular frequency. While the device is > + running at a particular frequency, CPR monitors dynamic factors such as > + temperature, etc. and suggests or, in the CPR-Hardened case performs, > + adjustments to the voltage to save power and meet silicon characteristic > + requirements. > + > +maintainers: > + - AngeloGioacchino Del Regno <angelogioacchino.delregno@xxxxxxxxxxxxx> > + > +properties: > + compatible: > + oneOf: > + - description: CPRv3 controller > + items: > + - const: qcom,cpr3 > + - description: CPRv4 controller > + items: > + - const: qcom,cpr4 > + - description: CPRv4-Hardened controller > + items: > + - enum: > + - qcom,msm8998-cprh > + - qcom,sdm630-cprh > + - const: qcom,cprh > + > + reg: > + description: Base address and size of the CPR controller(s) > + minItems: 1 > + maxItems: 2 > + > + interrupts: > + maxItems: 1 > + > + clock-names: > + items: > + - const: "ref" > + > + clocks: > + items: > + - description: CPR reference clock > + > + vdd-supply: > + description: Autonomous Phase Control (APC) or other power supply > + > + '#power-domain-cells': > + const: 1 > + > + acc-syscon: > + $ref: /schemas/types.yaml#/definitions/phandle > + description: phandle to syscon for writing ACC settings > + > + nvmem-cells: > + description: Cells containing the fuse corners and revision data > + minItems: 10 > + maxItems: 32 > + > + nvmem-cell-names: > + minItems: 10 > + maxItems: 32 > + > + operating-points-v2: true > + > +required: > + - compatible > + - reg > + - clock-names > + - clocks > + - "#power-domain-cells" > + - nvmem-cells > + - nvmem-cell-names > + - operating-points-v2 > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/qcom,gcc-msm8998.h> > + #include <dt-bindings/interrupt-controller/irq.h> > + > + cpus { > + #address-cells = <2>; > + #size-cells = <0>; > + > + cpu@0 { > + compatible = "qcom,kryo280"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + operating-points-v2 = <&cpu_gold_opp_table>; > + power-domains = <&apc_cprh 0>; > + power-domain-names = "cprh"; > + }; > + > + cpu@100 { > + compatible = "qcom,kryo280"; > + device_type = "cpu"; > + reg = <0x0 0x0>; > + operating-points-v2 = <&cpu_silver_opp_table>; > + power-domains = <&apc_cprh 1>; > + power-domain-names = "cprh"; > + }; > + }; > + > + cpu_gold_opp_table: opp-table-gold { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-2208000000 { > + opp-hz = /bits/ 64 <2208000000>; > + required-opps = <&cprh_opp3>; > + }; > + opp-1113600000 { > + opp-hz = /bits/ 64 <1113600000>; > + required-opps = <&cprh_opp2>; > + }; > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&cprh_opp1>; > + }; > + }; > + > + cpu_silver_opp_table: opp-table-silver { > + compatible = "operating-points-v2"; > + opp-shared; > + > + opp-1843200000 { > + opp-hz = /bits/ 64 <1843200000>; > + required-opps = <&cprh_opp3>; > + }; > + opp-1094400000 { > + opp-hz = /bits/ 64 <1094400000>; > + required-opps = <&cprh_opp2>; > + }; > + opp-300000000 { > + opp-hz = /bits/ 64 <300000000>; > + required-opps = <&cprh_opp1>; > + }; > + }; > + > + cprh_opp_table: opp-table-cprh { > + compatible = "operating-points-v2-qcom-level"; > + > + cprh_opp1: opp1 { > + opp-level = <1>; > + qcom,opp-fuse-level = <1>; > + }; > + cprh_opp2: opp2 { > + opp-level = <2>; > + qcom,opp-fuse-level = <2>; > + }; > + cprh_opp3: opp3 { > + opp-level = <3>; > + qcom,opp-fuse-level = <2 3>; > + }; > + }; > + > + apc_cprh: power-controller@179c8000 { > + compatible = "qcom,msm8998-cprh", "qcom,cprh"; > + reg = <0x0179c8000 0x4000>, <0x0179c4000 0x4000>; > + clocks = <&gcc GCC_HMSS_RBCPR_CLK>; > + clock-names = "ref"; > + > + #power-domain-cells = <1>; > + operating-points-v2 = <&cprh_opp_table>; > + > + nvmem-cells = <&cpr_efuse_speedbin>, > + <&cpr_fuse_revision>, > + <&cpr_quot0_pwrcl>, > + <&cpr_quot1_pwrcl>, > + <&cpr_quot2_pwrcl>, > + <&cpr_quot3_pwrcl>, > + <&cpr_quot_offset1_pwrcl>, > + <&cpr_quot_offset2_pwrcl>, > + <&cpr_quot_offset3_pwrcl>, > + <&cpr_init_voltage0_pwrcl>, > + <&cpr_init_voltage1_pwrcl>, > + <&cpr_init_voltage2_pwrcl>, > + <&cpr_init_voltage3_pwrcl>, > + <&cpr_ro_sel0_pwrcl>, > + <&cpr_ro_sel1_pwrcl>, > + <&cpr_ro_sel2_pwrcl>, > + <&cpr_ro_sel3_pwrcl>, > + <&cpr_quot0_perfcl>, > + <&cpr_quot1_perfcl>, > + <&cpr_quot2_perfcl>, > + <&cpr_quot3_perfcl>, > + <&cpr_quot_offset1_perfcl>, > + <&cpr_quot_offset2_perfcl>, > + <&cpr_quot_offset3_perfcl>, > + <&cpr_init_voltage0_perfcl>, > + <&cpr_init_voltage1_perfcl>, > + <&cpr_init_voltage2_perfcl>, > + <&cpr_init_voltage3_perfcl>, > + <&cpr_ro_sel0_perfcl>, > + <&cpr_ro_sel1_perfcl>, > + <&cpr_ro_sel2_perfcl>, > + <&cpr_ro_sel3_perfcl>; > + > + nvmem-cell-names = "cpr_speed_bin", > + "cpr_fuse_revision", > + "cpr0_quotient1", > + "cpr0_quotient2", > + "cpr0_quotient3", > + "cpr0_quotient4", > + "cpr0_quotient_offset2", > + "cpr0_quotient_offset3", > + "cpr0_quotient_offset4", > + "cpr0_init_voltage1", > + "cpr0_init_voltage2", > + "cpr0_init_voltage3", > + "cpr0_init_voltage4", > + "cpr0_ring_osc1", > + "cpr0_ring_osc2", > + "cpr0_ring_osc3", > + "cpr0_ring_osc4", > + "cpr1_quotient1", > + "cpr1_quotient2", > + "cpr1_quotient3", > + "cpr1_quotient4", > + "cpr1_quotient_offset2", > + "cpr1_quotient_offset3", > + "cpr1_quotient_offset4", > + "cpr1_init_voltage1", > + "cpr1_init_voltage2", > + "cpr1_init_voltage3", > + "cpr1_init_voltage4", > + "cpr1_ring_osc1", > + "cpr1_ring_osc2", > + "cpr1_ring_osc3", > + "cpr1_ring_osc4"; > + }; > +...
