On Mon, Dec 12, 2022 at 06:07:23PM +0000, Sudip Mukherjee wrote:
> If the spi transfer is using dual/quad/octal spi mode, then we need to
> update the SPI_CTRLR0 register. The SPI_CTRLR0 register will be updated
> in dw_spi_update_config() via the values in dw_spi_cfg.
>
> Signed-off-by: Sudip Mukherjee <sudip.mukherjee@xxxxxxxxxx>
> ---
>
> Note: DW_SPI_SPI_CTRLR0_INST_L_INST_L16 will not work yet as
> spi_mem_default_supports_op() checks for op->cmd.nbytes != 1.
>
> drivers/spi/spi-dw-core.c | 46 +++++++++++++++++++++++++++++++++++++++
> drivers/spi/spi-dw.h | 9 ++++++++
> 2 files changed, 55 insertions(+)
>
> diff --git a/drivers/spi/spi-dw-core.c b/drivers/spi/spi-dw-core.c
> index 89438ae2df17d..06169aa3f37bf 100644
> --- a/drivers/spi/spi-dw-core.c
> +++ b/drivers/spi/spi-dw-core.c
> @@ -836,10 +836,56 @@ static int dw_spi_exec_enh_mem_op(struct spi_mem *mem, const struct spi_mem_op *
> {
> struct spi_controller *ctlr = mem->spi->controller;
> struct dw_spi *dws = spi_controller_get_devdata(ctlr);
> + struct dw_spi_cfg cfg;
> +
> + switch (op->data.buswidth) {
> + case 2:
> + cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI;
> + break;
> + case 4:
> + cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI;
> + break;
> + case 8:
> + cfg.spi_frf = DW_SPI_CTRLR0_SPI_FRF_OCT_SPI;
> + break;
> + default:
> + return dw_spi_exec_mem_op(mem, op);
case 1:
return dw_spi_exec_mem_op(mem, op);
case 2:
cfg.enh_frf = DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI;
break;
...
default:
return -EINVAL;
> + }
>
> /* Collect cmd and addr into a single buffer */
> dw_spi_init_enh_mem_buf(dws, op);
>
> + cfg.dfs = 8;
> + cfg.freq = clamp(mem->spi->max_speed_hz, 0U, dws->max_mem_freq);
> + cfg.ndf = op->data.nbytes;
> + if (op->data.dir == SPI_MEM_DATA_IN)
> + cfg.tmode = DW_SPI_CTRLR0_TMOD_RO;
> + else
> + cfg.tmode = DW_SPI_CTRLR0_TMOD_TO;
Newline, please.
> + if (op->data.buswidth == op->addr.buswidth &&
> + op->data.buswidth == op->cmd.buswidth)
> + cfg.trans_t = DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT2;
> + else if (op->data.buswidth == op->addr.buswidth)
> + cfg.trans_t = DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT1;
> + else
> + cfg.trans_t = DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT0;
> +
> + cfg.addr_l = clamp(op->addr.nbytes * 2, 0, 0xf);
First the address length should be checked in the
spi_controller_mem_ops.supports_op method. Thus the clamping procedure
would be redundant. Second instead of using the multiplication
operator I would suggest to have the bitwise left-shift op utilized
here, (cfg.addr_l = op->addr.nbytes << 2). This shall look a bit more
coherent.
> + if (op->cmd.nbytes > 1)
> + cfg.inst_l = DW_SPI_SPI_CTRLR0_INST_L_INST_L16;
No. Firstly INST_L16 means 2-bytes length. Using greater-than op here
is incorrect. Secondly the command part length should be
checked in the spi_controller_mem_ops.supports_op callback.
> + else if (op->cmd.nbytes == 1)
> + cfg.inst_l = DW_SPI_SPI_CTRLR0_INST_L_INST_L8;
> + else
> + cfg.inst_l = DW_SPI_SPI_CTRLR0_INST_L_INST_L0;
> +
> + cfg.wait_c = (op->dummy.nbytes * (BITS_PER_BYTE / op->dummy.buswidth));
Hm, what if buswidth is zero?
> +
> + dw_spi_enable_chip(dws, 0);
> +
> + dw_spi_update_config(dws, mem->spi, &cfg);
> +
> + dw_spi_enable_chip(dws, 1);
> +
> return 0;
> }
>
> diff --git a/drivers/spi/spi-dw.h b/drivers/spi/spi-dw.h
> index 327d037bdb10e..494b830ad1026 100644
> --- a/drivers/spi/spi-dw.h
> +++ b/drivers/spi/spi-dw.h
> @@ -101,6 +101,9 @@
> #define DW_HSSI_CTRLR0_SPI_FRF_MASK GENMASK(23, 22)
> #define DW_PSSI_CTRLR0_SPI_FRF_MASK GENMASK(22, 21)
> #define DW_SPI_CTRLR0_SPI_FRF_STD_SPI 0x0
> +#define DW_SPI_CTRLR0_SPI_FRF_DUAL_SPI 0x1
> +#define DW_SPI_CTRLR0_SPI_FRF_QUAD_SPI 0x2
> +#define DW_SPI_CTRLR0_SPI_FRF_OCT_SPI 0x3
Please replace SPI_FRF with ENH_FRF and drop _SPI suffix from the
macros.
>
> /* Bit fields in CTRLR1 */
> #define DW_SPI_NDF_MASK GENMASK(15, 0)
> @@ -132,7 +135,13 @@
> #define DW_SPI_SPI_CTRLR0_CLK_STRETCH_EN BIT(30)
> #define DW_SPI_SPI_CTRLR0_WAIT_CYCLE_MASK GENMASK(15, 11)
> #define DW_SPI_SPI_CTRLR0_INST_L_MASK GENMASK(9, 8)
> +#define DW_SPI_SPI_CTRLR0_INST_L_INST_L0 0x0
> +#define DW_SPI_SPI_CTRLR0_INST_L_INST_L8 0x2
> +#define DW_SPI_SPI_CTRLR0_INST_L_INST_L16 0x3
> #define DW_SPI_SPI_CTRLR0_ADDR_L_MASK GENMASK(5, 2)
> +#define DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT0 0x0
> +#define DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT1 0x1
> +#define DW_SPI_SPI_CTRLR0_TRANS_TYPE_TT2 0x2
Please replace SPI_CTRLR0 with ENH_CTRLR0.
-Serge(y)
>
> /* Mem/DMA operations helpers */
> #define DW_SPI_WAIT_RETRIES 5
> --
> 2.30.2
>
