On 10/01/2023 09:32, Jim Liu wrote: > Add dt-bindings document for the Nuvoton NPCM7xx and NPCM8xx sgpio driver > > Signed-off-by: Jim Liu <jim.t90615@xxxxxxxxx> > --- > Changes for v4: > - modify in/out property > - modify bus-frequency property > Changes for v3: > - modify description > - modify in/out property name > Changes for v2: > - modify description > --- > .../bindings/gpio/nuvoton,sgpio.yaml | 92 +++++++++++++++++++ > 1 file changed, 92 insertions(+) > create mode 100644 Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml > > diff --git a/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml > new file mode 100644 > index 000000000000..3c01ce61f8d9 > --- /dev/null > +++ b/Documentation/devicetree/bindings/gpio/nuvoton,sgpio.yaml > @@ -0,0 +1,92 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/gpio/nuvoton,sgpio.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Nuvoton SGPIO controller > + > +maintainers: > + - Jim LIU <JJLIU0@xxxxxxxxxxx> > + > +description: > + This SGPIO controller is for NUVOTON NPCM7xx and NPCM8xx SoC. > + Nuvoton NPCM7xx SGPIO module is combine serial to parallel IC (HC595) > + and parallel to serial IC (HC165), and use APB3 clock to control it. > + This interface has 4 pins (D_out , D_in, S_CLK, LDSH). > + NPCM7xx/NPCM8xx have two sgpio module each module can support up > + to 64 output pins,and up to 64 input pin, the pin is only for gpi or gpo. > + GPIO pins have sequential, First half is gpo and second half is gpi. > + GPIO pins can be programmed to support the following options > + - Support interrupt option for each input port and various interrupt > + sensitivity option (level-high, level-low, edge-high, edge-low) > + - ngpios is number of nuvoton,input-ngpios GPIO lines and nuvoton,output-ngpios GPIO lines. > + nuvoton,input-ngpios GPIO lines is only for gpi. > + nuvoton,output-ngpios GPIO lines is only for gpo. > + > +properties: > + compatible: > + enum: > + - nuvoton,npcm750-sgpio > + - nuvoton,npcm845-sgpio > + > + reg: > + maxItems: 1 > + > + gpio-controller: true > + > + '#gpio-cells': > + const: 2 > + > + interrupts: > + maxItems: 1 > + > + clocks: > + maxItems: 1 > + > + nuvoton,input-ngpios: > + description: The numbers of GPIO's exposed. > + GPIO lines is only for gpi. > + minimum: 0 > + maximum: 64 > + > + nuvoton,output-ngpios: > + description: The numbers of GPIO's exposed. > + GPIO lines is only for gpo. > + minimum: 0 > + maximum: 64 > + > + bus-frequency: > + description: Directly connected to APB bus and > + its shift clock is from APB bus clock divided by a programmable value. The bus frequency is derived from input clocks, isn't it? We already questioned this property and this does not help justify it existence. Drop it. > + default: 8000000 > + > +required: > + - compatible > + - reg > + - gpio-controller > + - '#gpio-cells' > + - interrupts > + - nuvoton,input-ngpios > + - nuvoton,output-ngpios > + - clocks > + - bus-frequency > + > +additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/clock/nuvoton,npcm7xx-clock.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + gpio8: gpio@101000 { > + compatible = "nuvoton,npcm750-sgpio"; > + reg = <0x101000 0x200>; > + clocks = <&clk NPCM7XX_CLK_APB3>; > + interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>; > + bus-frequency = <8000000>; > + gpio-controller; > + #gpio-cells = <2>; > + nuvoton,input-ngpios = <64>; > + nuvoton,output-ngpios = <64>; > + status = "disabled"; I reminded you about this twice. So this is third time. Or maybe even fourth? Best regards, Krzysztof
