Re: [PATCH v2 6/7] drm/msm/dsi: add support for DSI-PHY on SM8550

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On Mon, 9 Jan 2023 at 11:38, Neil Armstrong <neil.armstrong@xxxxxxxxxx> wrote:
>
> On 09/01/2023 10:26, Neil Armstrong wrote:
> > SM8550 use a 4nm DSI PHYs, which share register definitions
> > with 7nm DSI PHYs. Rather than duplicating the driver, handle
> > 4nm variant inside the common 5+7nm driver.
> >
> > Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> > ---
> >   drivers/gpu/drm/msm/Kconfig               |  4 +-
> >   drivers/gpu/drm/msm/dsi/phy/dsi_phy.c     |  2 +
> >   drivers/gpu/drm/msm/dsi/phy/dsi_phy.h     |  1 +
> >   drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c | 88 ++++++++++++++++++++++++++-----
> >   4 files changed, 79 insertions(+), 16 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig
> > index e7b100d97f88..949b18a29a55 100644
> > --- a/drivers/gpu/drm/msm/Kconfig
> > +++ b/drivers/gpu/drm/msm/Kconfig
> > @@ -140,11 +140,11 @@ config DRM_MSM_DSI_10NM_PHY
> >         Choose this option if DSI PHY on SDM845 is used on the platform.
> >
> >   config DRM_MSM_DSI_7NM_PHY
> > -     bool "Enable DSI 7nm/5nm PHY driver in MSM DRM"
> > +     bool "Enable DSI 7nm/5nm/4nm PHY driver in MSM DRM"
> >       depends on DRM_MSM_DSI
> >       default y
> >       help
> > -       Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SC7280
> > +       Choose this option if DSI PHY on SM8150/SM8250/SM8350/SM8450/SM8550/SC7280
> >         is used on the platform.
> >
> >   config DRM_MSM_HDMI
> > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> > index 04126af74bb5..798cd3c86031 100644
> > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.c
> > @@ -573,6 +573,8 @@ static const struct of_device_id dsi_phy_dt_match[] = {
> >         .data = &dsi_phy_5nm_8350_cfgs },
> >       { .compatible = "qcom,sm8450-dsi-phy-5nm",
> >         .data = &dsi_phy_5nm_8450_cfgs },
> > +     { .compatible = "qcom,dsi-phy-4nm-8550",
>
> Forgot to change this... I can resend a v3 with this fixed.

Yes, please.

>
> Neil
>
> > +       .data = &dsi_phy_4nm_8550_cfgs },
> >   #endif
> >       {}
> >   };
> > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> > index f7a907ed2b4b..58f9e09f5224 100644
> > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy.h
> > @@ -59,6 +59,7 @@ extern const struct msm_dsi_phy_cfg dsi_phy_7nm_8150_cfgs;
> >   extern const struct msm_dsi_phy_cfg dsi_phy_7nm_7280_cfgs;
> >   extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8350_cfgs;
> >   extern const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs;
> > +extern const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs;
> >
> >   struct msm_dsi_dphy_timing {
> >       u32 clk_zero;
> > diff --git a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> > index 7b2c16b3a36c..af5c952c6ad0 100644
> > --- a/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> > +++ b/drivers/gpu/drm/msm/dsi/phy/dsi_phy_7nm.c
> > @@ -47,6 +47,8 @@
> >   #define DSI_PHY_7NM_QUIRK_V4_2              BIT(2)
> >   /* Hardware is V4.3 */
> >   #define DSI_PHY_7NM_QUIRK_V4_3              BIT(3)
> > +/* Hardware is V5.2 */
> > +#define DSI_PHY_7NM_QUIRK_V5_2               BIT(4)
> >
> >   struct dsi_pll_config {
> >       bool enable_ssc;
> > @@ -124,14 +126,25 @@ static void dsi_pll_calc_dec_frac(struct dsi_pll_7nm *pll, struct dsi_pll_config
> >
> >       if (pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_PRE_V4_1)
> >               config->pll_clock_inverters = 0x28;
> > -     else if (pll_freq <= 1000000000ULL)
> > -             config->pll_clock_inverters = 0xa0;
> > -     else if (pll_freq <= 2500000000ULL)
> > -             config->pll_clock_inverters = 0x20;
> > -     else if (pll_freq <= 3020000000ULL)
> > -             config->pll_clock_inverters = 0x00;
> > -     else
> > -             config->pll_clock_inverters = 0x40;
> > +     else if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> > +             if (pll_freq <= 1300000000ULL)
> > +                     config->pll_clock_inverters = 0xa0;
> > +             else if (pll_freq <= 2500000000ULL)
> > +                     config->pll_clock_inverters = 0x20;
> > +             else if (pll_freq <= 4000000000ULL)
> > +                     config->pll_clock_inverters = 0x00;
> > +             else
> > +                     config->pll_clock_inverters = 0x40;
> > +     } else {
> > +             if (pll_freq <= 1000000000ULL)
> > +                     config->pll_clock_inverters = 0xa0;
> > +             else if (pll_freq <= 2500000000ULL)
> > +                     config->pll_clock_inverters = 0x20;
> > +             else if (pll_freq <= 3020000000ULL)
> > +                     config->pll_clock_inverters = 0x00;
> > +             else
> > +                     config->pll_clock_inverters = 0x40;
> > +     }
> >
> >       config->decimal_div_start = dec;
> >       config->frac_div_start = frac;
> > @@ -222,6 +235,13 @@ static void dsi_pll_config_hzindep_reg(struct dsi_pll_7nm *pll)
> >                       vco_config_1 = 0x01;
> >       }
> >
> > +     if ((pll->phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> > +             if (pll->vco_current_rate < 1557000000ULL)
> > +                     vco_config_1 = 0x08;
> > +             else
> > +                     vco_config_1 = 0x01;
> > +     }
> > +
> >       dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_ANALOG_CONTROLS_FIVE_1,
> >                     analog_controls_five_1);
> >       dsi_phy_write(base + REG_DSI_7nm_PHY_PLL_VCO_CONFIG_1, vco_config_1);
> > @@ -860,7 +880,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> >               pr_warn("PLL turned on before configuring PHY\n");
> >
> >       /* Request for REFGEN READY */
> > -     if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> > +     if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
> > +         (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >               dsi_phy_write(phy->base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x1);
> >               udelay(500);
> >       }
> > @@ -894,7 +915,19 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> >               lane_ctrl0 = 0x1f;
> >       }
> >
> > -     if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> > +     if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> > +             if (phy->cphy_mode) {
> > +                     vreg_ctrl_0 = 0x45;
> > +                     vreg_ctrl_1 = 0x45;
> > +                     glbl_rescode_top_ctrl = 0x00;
> > +                     glbl_rescode_bot_ctrl = 0x00;
> > +             } else {
> > +                     vreg_ctrl_0 = 0x44;
> > +                     vreg_ctrl_1 = 0x19;
> > +                     glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3c :  0x03;
> > +                     glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 :  0x3c;
> > +             }
> > +     } else if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3)) {
> >               if (phy->cphy_mode) {
> >                       glbl_rescode_top_ctrl = less_than_1500_mhz ? 0x3d :  0x01;
> >                       glbl_rescode_bot_ctrl = less_than_1500_mhz ? 0x38 :  0x3b;
> > @@ -943,9 +976,8 @@ static int dsi_7nm_phy_enable(struct msm_dsi_phy *phy,
> >       dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_RBUF_CTRL, 0x00);
> >
> >       /* program CMN_CTRL_4 for minor_ver 2 chipsets*/
> > -     data = dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0);
> > -     data = data & (0xf0);
> > -     if (data == 0x20)
> > +     if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2) ||
> > +         (dsi_phy_read(base + REG_DSI_7nm_PHY_CMN_REVISION_ID0) & (0xf0)) == 0x20)
> >               dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_CTRL_4, 0x04);
> >
> >       /* Configure PHY lane swap (TODO: we need to calculate this) */
> > @@ -1058,7 +1090,8 @@ static void dsi_7nm_phy_disable(struct msm_dsi_phy *phy)
> >       dsi_phy_hw_v4_0_config_lpcdrx(phy, false);
> >
> >       /* Turn off REFGEN Vote */
> > -     if (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) {
> > +     if ((phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V4_3) ||
> > +         (phy->cfg->quirks & DSI_PHY_7NM_QUIRK_V5_2)) {
> >               dsi_phy_write(base + REG_DSI_7nm_PHY_CMN_GLBL_DIGTOP_SPARE10, 0x0);
> >               wmb();
> >               /* Delay to ensure HW removes vote before PHY shut down */
> > @@ -1092,6 +1125,10 @@ static const struct regulator_bulk_data dsi_phy_7nm_97800uA_regulators[] = {
> >       { .supply = "vdds", .init_load_uA = 97800 },
> >   };
> >
> > +static const struct regulator_bulk_data dsi_phy_7nm_98400uA_regulators[] = {
> > +     { .supply = "vdds", .init_load_uA = 98400 },
> > +};
> > +
> >   const struct msm_dsi_phy_cfg dsi_phy_7nm_cfgs = {
> >       .has_phy_lane = true,
> >       .regulator_data = dsi_phy_7nm_36mA_regulators,
> > @@ -1201,3 +1238,26 @@ const struct msm_dsi_phy_cfg dsi_phy_5nm_8450_cfgs = {
> >       .num_dsi_phy = 2,
> >       .quirks = DSI_PHY_7NM_QUIRK_V4_3,
> >   };
> > +
> > +const struct msm_dsi_phy_cfg dsi_phy_4nm_8550_cfgs = {
> > +     .has_phy_lane = true,
> > +     .regulator_data = dsi_phy_7nm_98400uA_regulators,
> > +     .num_regulators = ARRAY_SIZE(dsi_phy_7nm_98400uA_regulators),
> > +     .ops = {
> > +             .enable = dsi_7nm_phy_enable,
> > +             .disable = dsi_7nm_phy_disable,
> > +             .pll_init = dsi_pll_7nm_init,
> > +             .save_pll_state = dsi_7nm_pll_save_state,
> > +             .restore_pll_state = dsi_7nm_pll_restore_state,
> > +             .set_continuous_clock = dsi_7nm_set_continuous_clock,
> > +     },
> > +     .min_pll_rate = 600000000UL,
> > +#ifdef CONFIG_64BIT
> > +     .max_pll_rate = 5000000000UL,
> > +#else
> > +     .max_pll_rate = ULONG_MAX,
> > +#endif
> > +     .io_start = { 0xae95000, 0xae97000 },
> > +     .num_dsi_phy = 2,
> > +     .quirks = DSI_PHY_7NM_QUIRK_V5_2,
> > +};
> >
>


-- 
With best wishes
Dmitry



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