Hi Thierry, Uwe, Geert and PWM folks,
Gentle ping for review.
Cheers,
Biju
> -----Original Message-----
> From: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>
> Sent: 13 December 2022 18:58
> To: Thierry Reding <thierry.reding@xxxxxxxxx>; Rob Herring
> <robh+dt@xxxxxxxxxx>; Krzysztof Kozlowski
> <krzysztof.kozlowski+dt@xxxxxxxxxx>; Michael Turquette
> <mturquette@xxxxxxxxxxxx>; Stephen Boyd <sboyd@xxxxxxxxxx>; Philipp Zabel
> <p.zabel@xxxxxxxxxxxxxx>
> Cc: Biju Das <biju.das.jz@xxxxxxxxxxxxxx>; Uwe Kleine-König <u.kleine-
> koenig@xxxxxxxxxxxxxx>; Geert Uytterhoeven <geert+renesas@xxxxxxxxx>; Magnus
> Damm <magnus.damm@xxxxxxxxx>; linux-pwm@xxxxxxxxxxxxxxx;
> devicetree@xxxxxxxxxxxxxxx; linux-renesas-soc@xxxxxxxxxxxxxxx; linux-
> clk@xxxxxxxxxxxxxxx; Fabrizio Castro <fabrizio.castro.jz@xxxxxxxxxxx>
> Subject: [PATCH v3 0/4] Add RZ/V2{M, MA} PWM driver support
>
> The RZ/V2{M, MA} PWM Timer (PWM) is composed of 16 channels. Linux is only
> allowed access to channels 8 to 14 on RZ/V2M, while there is no restriction
> for RZ/V2MA.
>
> The RZ/V2{M, MA} PWM Timer (PWM) supports the following functions:
> * The PWM has 24-bit counters which operate at PWM_CLK (48 MHz).
> * The frequency division ratio for internal counter operation is selectable
> as PWM_CLK divided by 1, 16, 256, or 2048.
> * The period as well as the duty cycle is adjustable.
> * The low-level and high-level order of the PWM signals can be inverted.
> * The duty cycle of the PWM signal is selectable in the range from 0 to
> 100%.
> * The minimum resolution is 20.83 ns.
> * Three interrupt sources: Rising and falling edges of the PWM signal and
> clearing of the counter
> * Counter operation and the bus interface are asynchronous and both can
> operate independently of the magnitude relationship of the respective
> clock periods.
>
> v2->v3:
> * Removed clock patch#1 as it is queued for 6.3 renesas-clk
> * Added Rb tag from Geert for bindings and dt patches
> * Added return code for rzv2m_pwm_get_state()
> * Added comment in rzv2m_pwm_reset_assert_pm_disable()
> v1->v2:
> * Updated commit description
> * Replaced pwm8_15_pclk->cperi_grpf
> * Added reset entry R9A09G011_PWM_GPF_PRESETN
> * Added Rb tag from Krzysztof for bindings and the keep the Rb tag as
> the below changes are trivial
> * Updated the description for APB clock
> * Added resets required property
> * Updated the example with resets property
> * Replaced devm_reset_control_get_optional_shared-
> >devm_reset_control_get_shared
> * Added resets property in pwm nodes.
>
> Note:
> Hardware manual for this IP can be found here
> https://www.renesas.com/in/en/document/mah/rzv2m-users-manual-
> hardware?language=en
>
> Biju Das (4):
> dt-bindings: pwm: Add RZ/V2M PWM binding
> pwm: Add support for RZ/V2M PWM driver
> arm64: dts: renesas: r9a09g011: Add pwm nodes
> arm64: dts: renesas: rzv2m evk: Enable pwm
>
> .../bindings/pwm/renesas,rzv2m-pwm.yaml | 90 ++++
> .../boot/dts/renesas/r9a09g011-v2mevk2.dts | 70 +++
> arch/arm64/boot/dts/renesas/r9a09g011.dtsi | 98 +++++
> drivers/pwm/Kconfig | 11 +
> drivers/pwm/Makefile | 1 +
> drivers/pwm/pwm-rzv2m.c | 398 ++++++++++++++++++
> 6 files changed, 668 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/pwm/renesas,rzv2m-
> pwm.yaml
> create mode 100644 drivers/pwm/pwm-rzv2m.c
>
> --
> 2.25.1
