The new Broadcom Broadband BCMBCA SoCs includes a updated HSSPI controller. Add a new compatible string and required fields for the new driver. Also add myself and Kursad as the maintainers. Signed-off-by: William Zhang <william.zhang@xxxxxxxxxxxx> --- .../bindings/spi/brcm,bcm63xx-hsspi.yaml | 84 +++++++++++++++++-- 1 file changed, 78 insertions(+), 6 deletions(-) diff --git a/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml index 45f1417b1213..56e69d4a1faf 100644 --- a/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml +++ b/Documentation/devicetree/bindings/spi/brcm,bcm63xx-hsspi.yaml @@ -4,22 +4,51 @@ $id: http://devicetree.org/schemas/spi/brcm,bcm63xx-hsspi.yaml# $schema: http://devicetree.org/meta-schemas/core.yaml# -title: Broadcom BCM6328 High Speed SPI controller +title: Broadcom Broadband SoC High Speed SPI controller maintainers: + + - William Zhang <william.zhang@xxxxxxxxxxxx> + - Kursad Oney <kursad.oney@xxxxxxxxxxxx> - Jonas Gorski <jonas.gorski@xxxxxxxxx> +description: | + Broadcom Broadband SoC supports High Speed SPI master controller since the + early MIPS based chips such as BCM6328 and BCM63268. This controller was + carried over to recent ARM based chips, such as BCM63138, BCM4908 and BCM6858. + + It has a limitation that can not keep the chip select line active between + the SPI transfers within the same SPI message. This can terminate the + transaction to some SPI devices prematurely. The issue can be worked around by + either the controller's prepend mode or using the dummy chip select + workaround. This controller uses the compatible string brcm,bcm6328-hsspi. + + The newer SoCs such as BCM6756, BCM4912 and BCM6855 include an updated SPI + controller that add the capability to allow the driver to control chip select + explicitly. This solves the issue in the old controller. This new controller + uses the compatible string brcm,bcmbca-hsspi. + properties: compatible: - const: brcm,bcm6328-hsspi + enum: + - brcm,bcm6328-hsspi + - brcm,bcmbca-hsspi reg: - maxItems: 1 + items: + - description: main registers + - description: miscellaneous control registers + minItems: 1 + + reg-names: + items: + - const: hsspi + - const: spim-ctrl clocks: items: - - description: spi master reference clock - - description: spi master pll clock + - description: SPI master reference clock + - description: SPI master pll clock clock-names: items: @@ -29,12 +58,43 @@ properties: interrupts: maxItems: 1 + brcm,use-cs-workaround: + $ref: /schemas/types.yaml#/definitions/flag + description: | + Enable dummy chip select workaround for SPI transfers that can not be + supported by the default controller's prepend mode, i.e. delay or cs + change needed between SPI transfers. + required: - compatible - reg - clocks - clock-names - - interrupts + +allOf: + - $ref: "spi-controller.yaml#" + - if: + properties: + compatible: + contains: + enum: + - brcm,bcm6328-hsspi + then: + properties: + reg: + minItems: 1 + maxItems: 1 + else: + properties: + reg: + minItems: 2 + maxItems: 2 + reg-names: + minItems: 2 + maxItems: 2 + brcm,use-cs-workaround: false + required: + - reg-names unevaluatedProperties: false @@ -50,3 +110,15 @@ examples: #address-cells = <1>; #size-cells = <0>; }; + - | + spi@ff801000 { + compatible = "brcm,bcmbca-hsspi"; + reg = <0xff801000 0x1000>, + <0xff802610 0x4>; + reg-names = "hsspi", "spim-ctrl"; + clocks = <&hsspi>, <&hsspi_pll>; + clock-names = "hsspi", "pll"; + num-cs = <8>; + #address-cells = <1>; + #size-cells = <0>; + }; -- 2.37.3
