Add the Embedded USB Debugger(EUD) device tree node for SM6115 / SM4250 SoC. The node contains EUD base register region, EUD mode manager register region and TCSR Check register region along with the interrupt entry. Also add the typec connector node for EUD which is attached to EUD node via port. EUD is also attached to DWC3 node via port. To enable the role switch, we need to set dr_mode = "otg" property for 'usb_dwc3' sub-node in the board dts file. Also the EUD device can be enabled on a board once linux is boot'ed by setting: $ echo 1 > /sys/bus/platform/drivers/qcom_eud/../enable Cc: Souradeep Chowdhury <quic_schowdhu@xxxxxxxxxxx> Signed-off-by: Bhupesh Sharma <bhupesh.sharma@xxxxxxxxxx> --- - v2 can be viewed here: https://lore.kernel.org/linux-arm-msm/20230104052047.3945983-1-bhupesh.sharma@xxxxxxxxxx - In v3, fix the errors reported by '$ make dtbs_check' for the port sub node: ports: 'oneOf' conditional failed, one must be fixed: 'port' is a required property '#address-cells' is a required property '#size-cells' is a required property - This patch is based on my earlier sm6115 usb related changes, which can be seen here: https://lore.kernel.org/linux-arm-msm/20221215094532.589291-1-bhupesh.sharma@xxxxxxxxxx/ - This patch is also dependent on my sm6115 eud dt-binding and driver changes (v2) sent earlier, which can be seen here: https://lore.kernel.org/linux-arm-msm/20230103150419.3923421-1-bhupesh.sharma@xxxxxxxxxx/ arch/arm64/boot/dts/qcom/sm6115.dtsi | 46 ++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+) diff --git a/arch/arm64/boot/dts/qcom/sm6115.dtsi b/arch/arm64/boot/dts/qcom/sm6115.dtsi index 030763187cc3f..a1a4f659587f3 100644 --- a/arch/arm64/boot/dts/qcom/sm6115.dtsi +++ b/arch/arm64/boot/dts/qcom/sm6115.dtsi @@ -170,6 +170,18 @@ core3 { }; }; + eud_typec: connector { + compatible = "usb-c-connector"; + + ports { + port@0 { + con_eud: endpoint { + remote-endpoint = <&eud_con>; + }; + }; + }; + }; + firmware { scm: scm { compatible = "qcom,scm-sm6115", "qcom,scm"; @@ -565,6 +577,33 @@ gcc: clock-controller@1400000 { #power-domain-cells = <1>; }; + eud: eud@1610000 { + compatible = "qcom,sm6115-eud", "qcom,eud"; + reg = <0x01610000 0x2000>, + <0x01612000 0x1000>, + <0x003e5018 0x4>; + interrupts = <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + port@0 { + reg = <0>; + eud_ep: endpoint { + remote-endpoint = <&usb2_role_switch>; + }; + }; + + port@1 { + reg = <1>; + eud_con: endpoint { + remote-endpoint = <&con_eud>; + }; + }; + }; + }; + usb_hsphy: phy@1613000 { compatible = "qcom,sm6115-qusb2-phy"; reg = <0x01613000 0x180>; @@ -1064,6 +1103,13 @@ usb_dwc3: usb@4e00000 { snps,has-lpm-erratum; snps,hird-threshold = /bits/ 8 <0x10>; snps,usb3_lpm_capable; + usb-role-switch; + + port { + usb2_role_switch: endpoint { + remote-endpoint = <&eud_ep>; + }; + }; }; }; -- 2.38.1
