D1 contains an IOMMU for its video-related hardware. Add the node, and
hook it up to the masters which are already described in the devicetree.
Signed-off-by: Samuel Holland <samuel@xxxxxxxxxxxx>
---
Changes in v2:
- New patch for v2
arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
index dff363a3c934..ade50f1e01a4 100644
--- a/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
+++ b/arch/riscv/boot/dts/allwinner/sunxi-d1s-t113.dtsi
@@ -138,6 +138,14 @@ ccu: clock-controller@2001000 {
#reset-cells = <1>;
};
+ iommu: iommu@2010000 {
+ compatible = "allwinner,sun20i-d1-iommu";
+ reg = <0x2010000 0x10000>;
+ interrupts = <SOC_PERIPHERAL_IRQ(64) IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&ccu CLK_BUS_IOMMU>;
+ #iommu-cells = <1>;
+ };
+
dmic: dmic@2031000 {
compatible = "allwinner,sun20i-d1-dmic",
"allwinner,sun50i-h6-dmic";
@@ -574,6 +582,7 @@ mixer0: mixer@5100000 {
<&display_clocks CLK_MIXER0>;
clock-names = "bus", "mod";
resets = <&display_clocks RST_MIXER0>;
+ iommus = <&iommu 2>;
ports {
#address-cells = <1>;
@@ -596,6 +605,7 @@ mixer1: mixer@5200000 {
<&display_clocks CLK_MIXER1>;
clock-names = "bus", "mod";
resets = <&display_clocks RST_MIXER1>;
+ iommus = <&iommu 2>;
ports {
#address-cells = <1>;
--
2.37.4
