On 30/12/2022 21:22, Abel Vesa wrote:
> Add base dtsi for SM8550 SoC and includes base description of
> CPUs, GCC, RPMHCC, UART, interrupt controller, TLMM, reserved
> memory, RPMh PD, TCSRCC, ITS, IPCC, AOSS QMP, LLCC, cpufreq,
> interconnect, thermal sensor, cpu cooling maps and SMMU nodes
> which helps boot to shell with console on boards with this SoC.
>
> Co-developed-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> Signed-off-by: Neil Armstrong <neil.armstrong@xxxxxxxxxx>
> Signed-off-by: Abel Vesa <abel.vesa@xxxxxxxxxx>
> Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
> Reviewed-by: Sai Prakash Ranjan <quic_saipraka@xxxxxxxxxxx>
> ---
> arch/arm64/boot/dts/qcom/sm8550.dtsi | 3519 ++++++++++++++++++++++++++
> 1 file changed, 3519 insertions(+)
> create mode 100644 arch/arm64/boot/dts/qcom/sm8550.dtsi
>
> diff --git a/arch/arm64/boot/dts/qcom/sm8550.dtsi b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> new file mode 100644
> index 000000000000..a9514fcd6109
> --- /dev/null
> +++ b/arch/arm64/boot/dts/qcom/sm8550.dtsi
> @@ -0,0 +1,3519 @@
> +// SPDX-License-Identifier: BSD-3-Clause
> +/*
> + * Copyright (c) 2022, Linaro Limited
> + */
> +
> +#include <dt-bindings/clock/qcom,rpmh.h>
> +#include <dt-bindings/clock/qcom,sm8550-gcc.h>
> +#include <dt-bindings/clock/qcom,sm8550-tcsr.h>
> +#include <dt-bindings/dma/qcom-gpi.h>
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/interrupt-controller/arm-gic.h>
> +#include <dt-bindings/interconnect/qcom,sm8550-rpmh.h>
> +#include <dt-bindings/mailbox/qcom-ipcc.h>
> +#include <dt-bindings/power/qcom-rpmpd.h>
> +#include <dt-bindings/soc/qcom,rpmh-rsc.h>
> +#include <dt-bindings/thermal/thermal.h>
> +
> +/ {
> + interrupt-parent = <&intc>;
> +
> + #address-cells = <2>;
> + #size-cells = <2>;
> +
> + chosen { };
> +
> + clocks {
> + xo_board: xo-board {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> +
> + sleep_clk: sleep-clk {
> + compatible = "fixed-clock";
> + #clock-cells = <0>;
> + };
> + };
> +
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + CPU0: cpu@0 {
> + device_type = "cpu";
> + compatible = "qcom,kryo";
> + reg = <0 0>;
> + enable-method = "psci";
> + next-level-cache = <&L2_0>;
> + power-domains = <&CPU_PD0>;
> + power-domain-names = "psci";
> + qcom,freq-domain = <&cpufreq_hw 0>;
> + capacity-dmips-mhz = <1024>;
> + dynamic-power-coefficient = <100>;
> + #cooling-cells = <2>;
> + L2_0: l2-cache {
> + compatible = "cache";
You miss cache-level properties in all cache nodes.
> + next-level-cache = <&L3_0>;
> + L3_0: l3-cache {
Messed indentation,
> + compatible = "cache";
> + };
> + };
> + };
> +
Best regards,
Krzysztof
