On Fri, 30 Dec 2022 20:35:41 +0000,
Bernhard Rosenkränzer <bero@xxxxxxxxxxxx> wrote:
>
> From: Fabien Parent <fparent@xxxxxxxxxxxx>
>
> This adds minimal support for the Mediatek 8365 SOC and the EVK reference
> board, allowing the board to boot to initramfs with serial port I/O.
>
> Signed-off-by: Fabien Parent <fparent@xxxxxxxxxxxx>
> [bero@xxxxxxxxxxxx: Removed parts depending on drivers that aren't upstream yet, cleanups, add CPU cache layout, add systimer]
> Signed-off-by: Bernhard Rosenkränzer <bero@xxxxxxxxxxxx>
> Tested-by: Kevin Hilman <khilman@xxxxxxxxxxxx>
[...]
> + soc {
> + #address-cells = <2>;
> + #size-cells = <2>;
> + compatible = "simple-bus";
> + ranges;
> +
> + gic: interrupt-controller@c000000 {
> + compatible = "arm,gic-v3";
> + #interrupt-cells = <4>;
Why 4 cells? All the SPIs routed via sysirq are perfectly happy with 3
cells, and all the PPIs have 0 for the 4th cell (none of them use any
form of partitioning that'd require 4 cells). So where is this coming
from?
> + interrupt-parent = <&gic>;
> + interrupt-controller;
> + reg = <0 0x0c000000 0 0x80000>, <0 0x0c080000 0 0x80000>;
> +
The first region is obviously wrong (512kB for the distributor?
that's... most generous, but the architecture states that it is 64kB,
and that's wasteful enough).
This is also missing the GICC/GICH/GICV regions that Cortex-A53
implements, and that must be provided as per the binding.
> + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
> + };
Thanks,
M.
--
Without deviation from the norm, progress is not possible.
