Hey Icenowy, Hal
On 29 December 2022 05:25:00 GMT, Icenowy Zheng <uwu@xxxxxxxxxx> wrote:
>在 2022-12-28星期三的 22:48 +0000，Conor Dooley写道：
>> Hey,
>>
>> On Tue, Dec 20, 2022 at 09:12:46AM +0800, Hal Feng wrote:
>> > From: Emil Renner Berthing <kernel@xxxxxxxx>
>> >
>> > Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> > Technology Ltd.
>> >
>> > Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx>
>> > Co-developed-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
>> > Signed-off-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
>> > Co-developed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
>> > Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
>> > ---
>> > arch/riscv/boot/dts/starfive/jh7110.dtsi | 411
>> > +++++++++++++++++++++++
>> > 1 file changed, 411 insertions(+)
>> > create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>> >
>> > diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > new file mode 100644
>> > index 000000000000..64d260ea1f29
>> > --- /dev/null
>> > +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> > @@ -0,0 +1,411 @@
>> > +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> > +/*
>> > + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> > + * Copyright (C) 2022 Emil Renner Berthing <kernel@xxxxxxxx>
>> > + */
>> > +
>> > +/dts-v1/;
>> > +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> > +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> > +
>> > +/ {
>> > + compatible = "starfive,jh7110";
>> > + #address-cells = <2>;
>> > + #size-cells = <2>;
>> > +
>> > + cpus {
>> > + #address-cells = <1>;
>> > + #size-cells = <0>;
>> > +
>> > + S76_0: cpu@0 {
>> > + compatible = "sifive,u74-mc", "riscv";
>>
>> The label here says S76 but the compatible says u74-mc.
>> Which is correct? Your docs say S7 and S76, so I would imagine that
>> it
>> is actually an S76?
>>
>> > + reg = <0>;
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <8192>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <40>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <16384>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <40>;
>> > + mmu-type = "riscv,sv39";
>> > + next-level-cache = <&ccache>;
>> > + riscv,isa = "rv64imac";
>>
>> While I was poking around trying to see if there was some logic
>> behind
>> that compatible, I noticed that SiFive's docs for the S76 say it is
>> RV64GBC *but* the docs for the u74-mc say "4xRV64GBC and 1xRV64IMAC".
>> I assume that rv64imac is the correct one here?
>>
>> > + tlb-split;
>> > + status = "disabled";
>> > +
>> > + cpu0_intc: interrupt-controller {
>> > + compatible = "riscv,cpu-intc";
>> > + interrupt-controller;
>> > + #interrupt-cells = <1>;
>> > + };
>> > + };
>> > +
>> > + U74_1: cpu@1 {
>> > + compatible = "sifive,u74-mc", "riscv";
>> > + reg = <1>;
>> > + d-cache-block-size = <64>;
>> > + d-cache-sets = <64>;
>> > + d-cache-size = <32768>;
>> > + d-tlb-sets = <1>;
>> > + d-tlb-size = <40>;
>> > + device_type = "cpu";
>> > + i-cache-block-size = <64>;
>> > + i-cache-sets = <64>;
>> > + i-cache-size = <32768>;
>> > + i-tlb-sets = <1>;
>> > + i-tlb-size = <40>;
>> > + mmu-type = "riscv,sv39";
>> > + next-level-cache = <&ccache>;
>> > + riscv,isa = "rv64imafdc";
>>
>> That also begs the question:
>> Do your u74s support RV64GBC, as the (current) SiFive documentation
>> suggests?
>
>It supports RV64GCZbaZbb.
Sweet, thanks.
>B is not a well-defined thing by specifications, so it should be
>prevented here.
Yah, don't worry - my next question was going to be which bits were supported :)
Hal, can you update the isa string in the next version please?
Thanks,
Conor.
