On 28.12.2022 14:32, Dmitry Baryshkov wrote:
> The test clock apparently it's not used by anyone upstream. Remove it.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/clk/qcom/mmcc-msm8998.c | 25 -------------------------
> 1 file changed, 25 deletions(-)
>
> diff --git a/drivers/clk/qcom/mmcc-msm8998.c b/drivers/clk/qcom/mmcc-msm8998.c
> index c421b1291651..4490594bde69 100644
> --- a/drivers/clk/qcom/mmcc-msm8998.c
> +++ b/drivers/clk/qcom/mmcc-msm8998.c
> @@ -44,7 +44,6 @@ enum {
> P_HDMIPLL,
> P_DPVCO,
> P_DPLINK,
> - P_CORE_BI_PLL_TEST_SE,
> };
>
> static struct clk_fixed_factor gpll0_div = {
> @@ -303,69 +302,59 @@ static struct clk_alpha_pll_postdiv mmpll10_out_even = {
> static const struct parent_map mmss_xo_hdmi_map[] = {
> { P_XO, 0 },
> { P_HDMIPLL, 1 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_hdmi[] = {
> { .fw_name = "xo" },
> { .fw_name = "hdmipll" },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
> { P_XO, 0 },
> { P_DSI0PLL, 1 },
> { P_DSI1PLL, 2 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
> { .fw_name = "xo" },
> { .fw_name = "dsi0dsi" },
> { .fw_name = "dsi1dsi" },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_dsibyte_map[] = {
> { P_XO, 0 },
> { P_DSI0PLL_BYTE, 1 },
> { P_DSI1PLL_BYTE, 2 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_dsibyte[] = {
> { .fw_name = "xo" },
> { .fw_name = "dsi0byte" },
> { .fw_name = "dsi1byte" },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_dp_map[] = {
> { P_XO, 0 },
> { P_DPLINK, 1 },
> { P_DPVCO, 2 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_dp[] = {
> { .fw_name = "xo" },
> { .fw_name = "dplink" },
> { .fw_name = "dpvco" },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
> { P_XO, 0 },
> { P_GPLL0, 5 },
> { P_GPLL0_DIV, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
> { .fw_name = "xo" },
> { .fw_name = "gpll0" },
> { .hw = &gpll0_div.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
> @@ -373,7 +362,6 @@ static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
> { P_MMPLL0_OUT_EVEN, 1 },
> { P_GPLL0, 5 },
> { P_GPLL0_DIV, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
> @@ -381,7 +369,6 @@ static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
> { .hw = &mmpll0_out_even.clkr.hw },
> { .fw_name = "gpll0" },
> { .hw = &gpll0_div.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
> @@ -390,7 +377,6 @@ static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
> { P_MMPLL1_OUT_EVEN, 2 },
> { P_GPLL0, 5 },
> { P_GPLL0_DIV, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
> @@ -399,7 +385,6 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
> { .hw = &mmpll1_out_even.clkr.hw },
> { .fw_name = "gpll0" },
> { .hw = &gpll0_div.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
> @@ -408,7 +393,6 @@ static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
> { P_MMPLL5_OUT_EVEN, 2 },
> { P_GPLL0, 5 },
> { P_GPLL0_DIV, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
> @@ -417,7 +401,6 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
> { .hw = &mmpll5_out_even.clkr.hw },
> { .fw_name = "gpll0" },
> { .hw = &gpll0_div.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
> @@ -427,7 +410,6 @@ static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[
> { P_MMPLL6_OUT_EVEN, 4 },
> { P_GPLL0, 5 },
> { P_GPLL0_DIV, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
> @@ -437,7 +419,6 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div
> { .hw = &mmpll6_out_even.clkr.hw },
> { .fw_name = "gpll0" },
> { .hw = &gpll0_div.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
> @@ -447,7 +428,6 @@ static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map
> { P_MMPLL10_OUT_EVEN, 3 },
> { P_GPLL0, 5 },
> { P_GPLL0_DIV, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
> @@ -457,7 +437,6 @@ static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_di
> { .hw = &mmpll10_out_even.clkr.hw },
> { .fw_name = "gpll0" },
> { .hw = &gpll0_div.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
> @@ -467,7 +446,6 @@ static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map
> { P_MMPLL10_OUT_EVEN, 3 },
> { P_GPLL0, 5 },
> { P_GPLL0_DIV, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
> @@ -477,7 +455,6 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_di
> { .hw = &mmpll10_out_even.clkr.hw },
> { .fw_name = "gpll0" },
> { .hw = &gpll0_div.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
> @@ -488,7 +465,6 @@ static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_
> { P_MMPLL10_OUT_EVEN, 4 },
> { P_GPLL0, 5 },
> { P_GPLL0_DIV, 6 },
> - { P_CORE_BI_PLL_TEST_SE, 7 }
> };
>
> static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
> @@ -499,7 +475,6 @@ static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_g
> { .hw = &mmpll10_out_even.clkr.hw },
> { .fw_name = "gpll0" },
> { .hw = &gpll0_div.hw },
> - { .fw_name = "core_bi_pll_test_se" },
> };
>
> static struct clk_rcg2 byte0_clk_src = {
