On 27.12.2022 02:32, Dmitry Baryshkov wrote:
> Use ARRAY_SIZE() instead of manually specifying num_parents. This makes
> adding/removing entries to/from parent_data easy and errorproof.
>
> Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@xxxxxxxxxx>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@xxxxxxxxxx>
Konrad
> drivers/clk/qcom/mmcc-apq8084.c | 88 ++++++++++++++++-----------------
> 1 file changed, 44 insertions(+), 44 deletions(-)
>
> diff --git a/drivers/clk/qcom/mmcc-apq8084.c b/drivers/clk/qcom/mmcc-apq8084.c
> index e9f971359155..4acbcb43927f 100644
> --- a/drivers/clk/qcom/mmcc-apq8084.c
> +++ b/drivers/clk/qcom/mmcc-apq8084.c
> @@ -319,7 +319,7 @@ static struct clk_rcg2 mmss_ahb_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmss_ahb_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -344,7 +344,7 @@ static struct clk_rcg2 mmss_axi_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mmss_axi_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -368,7 +368,7 @@ static struct clk_rcg2 ocmemnoc_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "ocmemnoc_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -387,7 +387,7 @@ static struct clk_rcg2 csi0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -400,7 +400,7 @@ static struct clk_rcg2 csi1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -413,7 +413,7 @@ static struct clk_rcg2 csi2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi2_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -426,7 +426,7 @@ static struct clk_rcg2 csi3_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi3_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -456,7 +456,7 @@ static struct clk_rcg2 vfe0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vfe0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -469,7 +469,7 @@ static struct clk_rcg2 vfe1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vfe1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -497,7 +497,7 @@ static struct clk_rcg2 mdp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mdp_clk_src",
> .parent_names = mmcc_xo_mmpll0_dsi_hdmi_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_dsi_hdmi_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -509,7 +509,7 @@ static struct clk_rcg2 gfx3d_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "gfx3d_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_2_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_2_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -532,7 +532,7 @@ static struct clk_rcg2 jpeg0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -545,7 +545,7 @@ static struct clk_rcg2 jpeg1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -558,7 +558,7 @@ static struct clk_rcg2 jpeg2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "jpeg2_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -571,7 +571,7 @@ static struct clk_rcg2 pclk0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pclk0_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_pixel_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -585,7 +585,7 @@ static struct clk_rcg2 pclk1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "pclk1_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_pixel_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -610,7 +610,7 @@ static struct clk_rcg2 vcodec0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vcodec0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_3_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_3_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -629,7 +629,7 @@ static struct clk_rcg2 vp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vp_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -648,7 +648,7 @@ static struct clk_rcg2 cci_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cci_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -672,7 +672,7 @@ static struct clk_rcg2 camss_gp0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
> - .num_parents = 7,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -686,7 +686,7 @@ static struct clk_rcg2 camss_gp1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "camss_gp1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0_sleep,
> - .num_parents = 7,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0_sleep),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -714,7 +714,7 @@ static struct clk_rcg2 mclk0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk0_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -728,7 +728,7 @@ static struct clk_rcg2 mclk1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk1_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -742,7 +742,7 @@ static struct clk_rcg2 mclk2_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk2_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -756,7 +756,7 @@ static struct clk_rcg2 mclk3_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "mclk3_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll1_0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll1_0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -775,7 +775,7 @@ static struct clk_rcg2 csi0phytimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi0phytimer_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -788,7 +788,7 @@ static struct clk_rcg2 csi1phytimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi1phytimer_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -801,7 +801,7 @@ static struct clk_rcg2 csi2phytimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "csi2phytimer_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -824,7 +824,7 @@ static struct clk_rcg2 cpp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "cpp_clk_src",
> .parent_names = mmcc_xo_mmpll0_1_4_gpll0,
> - .num_parents = 5,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_1_4_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -836,7 +836,7 @@ static struct clk_rcg2 byte0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "byte0_clk_src",
> .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_byte2_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -849,7 +849,7 @@ static struct clk_rcg2 byte1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "byte1_clk_src",
> .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_byte2_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -868,7 +868,7 @@ static struct clk_rcg2 edpaux_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edpaux_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -887,7 +887,7 @@ static struct clk_rcg2 edplink_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edplink_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -907,7 +907,7 @@ static struct clk_rcg2 edppixel_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "edppixel_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp),
> .ops = &clk_edp_pixel_ops,
> },
> };
> @@ -925,7 +925,7 @@ static struct clk_rcg2 esc0_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "esc0_clk_src",
> .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -938,7 +938,7 @@ static struct clk_rcg2 esc1_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "esc1_clk_src",
> .parent_names = mmcc_xo_dsibyte_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsibyte_hdmi_edp_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -956,7 +956,7 @@ static struct clk_rcg2 extpclk_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "extpclk_clk_src",
> .parent_names = mmcc_xo_dsi_hdmi_edp_gpll0,
> - .num_parents = 6,
> + .num_parents = ARRAY_SIZE(mmcc_xo_dsi_hdmi_edp_gpll0),
> .ops = &clk_byte_ops,
> .flags = CLK_SET_RATE_PARENT,
> },
> @@ -975,7 +975,7 @@ static struct clk_rcg2 hdmi_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "hdmi_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -993,7 +993,7 @@ static struct clk_rcg2 vsync_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vsync_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1011,7 +1011,7 @@ static struct clk_rcg2 rbcpr_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "rbcpr_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1029,7 +1029,7 @@ static struct clk_rcg2 rbbmtimer_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "rbbmtimer_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1052,7 +1052,7 @@ static struct clk_rcg2 maple_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "maple_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1074,7 +1074,7 @@ static struct clk_rcg2 vdp_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vdp_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
> @@ -1093,7 +1093,7 @@ static struct clk_rcg2 vpu_bus_clk_src = {
> .clkr.hw.init = &(struct clk_init_data){
> .name = "vpu_bus_clk_src",
> .parent_names = mmcc_xo_mmpll0_mmpll1_gpll0,
> - .num_parents = 4,
> + .num_parents = ARRAY_SIZE(mmcc_xo_mmpll0_mmpll1_gpll0),
> .ops = &clk_rcg2_ops,
> },
> };
