Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC

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Subject: Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
From: Krzysztof Kozlowski <krzysztof.kozlowski@xxxxxxxxxx>
Date: Tue, 27 Dec 2022 08:58:01 +0100
Cc: linux-riscv@xxxxxxxxxxxxxxxxxxx, devicetree@xxxxxxxxxxxxxxx, Palmer Dabbelt <palmer@xxxxxxxxxxx>, Rob Herring <robh+dt@xxxxxxxxxx>, Krzysztof Kozlowski <krzysztof.kozlowski+dt@xxxxxxxxxx>, Paul Walmsley <paul.walmsley@xxxxxxxxxx>, Albert Ou <aou@xxxxxxxxxxxxxxxxx>, Ben Dooks <ben.dooks@xxxxxxxxxx>, Daniel Lezcano <daniel.lezcano@xxxxxxxxxx>, Thomas Gleixner <tglx@xxxxxxxxxxxxx>, Marc Zyngier <maz@xxxxxxxxxx>, Stephen Boyd <sboyd@xxxxxxxxxx>, Michael Turquette <mturquette@xxxxxxxxxxxx>, Philipp Zabel <p.zabel@xxxxxxxxxxxxxx>, Linus Walleij <linus.walleij@xxxxxxxxxx>, Emil Renner Berthing <emil.renner.berthing@xxxxxxxxxxxxx>, linux-kernel@xxxxxxxxxxxxxxx
In-reply-to: <Y6on34WC2u3PSBHl@spud>
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On 27/12/2022 00:01, Conor Dooley wrote:
> On Tue, Dec 20, 2022 at 09:12:40AM +0800, Hal Feng wrote:
> The DT is waiting for the clock/reset & pinctrl binding headers anyway,

Which were sent with build warnings/errors...

Best regards,
Krzysztof

Follow-Ups:
- Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
  - From: Conor Dooley

References:
- [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
  - From: Hal Feng
- Re: [PATCH v3 0/7] Basic device tree support for StarFive JH7110 RISC-V SoC
  - From: Conor Dooley

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