On Mon, 26 Dec 2022 at 12:08, Anand Moon <anand@xxxxxxxxxx> wrote:
>
> Rockchip RV1126 has GMAC 10/100/1000M ethernet controller.
> Enable ethernet node on Neu2-IO board.
>
> Signed-off-by: Anand Moon <anand@xxxxxxxxxx>
> ---
> drop SoB of Jagan Teki
> ---
> arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts | 37 ++++++++++++++++++++
> 1 file changed, 37 insertions(+)
>
> diff --git a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
> index dded0a12f0cd..bd592026eae6 100644
> --- a/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
> +++ b/arch/arm/boot/dts/rv1126-edgeble-neu2-io.dts
> @@ -22,6 +22,43 @@ chosen {
> };
> };
>
> +&gmac {
> + clock_in_out = "input";
> + pinctrl-names = "default";
> + pinctrl-0 = <&rgmiim1_pins &clk_out_ethernetm1_pins>;
> + phy-mode = "rgmii";
> + phy-handle = <&phy>;
arch/arm/boot/dts/rv1126-edgeble-neu2-io.dtb: phy@0: '#phy-cells' is a
required property From schema:
/home/j/.local/lib/python3.8/site-packages/dtschema/schemas/phy/phy-provider.yaml
> + assigned-clocks = <&cru CLK_GMAC_SRC>, <&cru CLK_GMAC_TX_RX>,
> + <&cru CLK_GMAC_ETHERNET_OUT>;
> + assigned-clock-parents = <&cru CLK_GMAC_SRC_M1>, <&cru RGMII_MODE_CLK>;
> + assigned-clock-rates = <125000000>, <0>, <25000000>;
Keep them in sorting order.
Jagan.
