On Tue, 20 Dec 2022 11:10:11 +0100, Krzysztof Kozlowski wrote:
> On 20/12/2022 02:12, Hal Feng wrote:
>> From: Emil Renner Berthing <kernel@xxxxxxxx>
>>
>> Add initial device tree for the JH7110 RISC-V SoC by StarFive
>> Technology Ltd.
>>
>> Signed-off-by: Emil Renner Berthing <kernel@xxxxxxxx>
>> Co-developed-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
>> Signed-off-by: Jianlong Huang <jianlong.huang@xxxxxxxxxxxxxxxx>
>> Co-developed-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
>> Signed-off-by: Hal Feng <hal.feng@xxxxxxxxxxxxxxxx>
>> ---
>> arch/riscv/boot/dts/starfive/jh7110.dtsi | 411 +++++++++++++++++++++++
>> 1 file changed, 411 insertions(+)
>> create mode 100644 arch/riscv/boot/dts/starfive/jh7110.dtsi
>>
>> diff --git a/arch/riscv/boot/dts/starfive/jh7110.dtsi b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> new file mode 100644
>> index 000000000000..64d260ea1f29
>> --- /dev/null
>> +++ b/arch/riscv/boot/dts/starfive/jh7110.dtsi
>> @@ -0,0 +1,411 @@
>> +// SPDX-License-Identifier: GPL-2.0 OR MIT
>> +/*
>> + * Copyright (C) 2022 StarFive Technology Co., Ltd.
>> + * Copyright (C) 2022 Emil Renner Berthing <kernel@xxxxxxxx>
>> + */
>> +
>> +/dts-v1/;
>> +#include <dt-bindings/clock/starfive,jh7110-crg.h>
>> +#include <dt-bindings/reset/starfive,jh7110-crg.h>
>> +
>> +/ {
>> + compatible = "starfive,jh7110";
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> +
>> + cpus {
>> + #address-cells = <1>;
>> + #size-cells = <0>;
>> +
>> + S76_0: cpu@0 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <0>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <8192>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <16384>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imac";
>> + tlb-split;
>> + status = "disabled";
>> +
>> + cpu0_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_1: cpu@1 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <1>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu1_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_2: cpu@2 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <2>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu2_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_3: cpu@3 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <3>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu3_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + U74_4: cpu@4 {
>> + compatible = "sifive,u74-mc", "riscv";
>> + reg = <4>;
>> + d-cache-block-size = <64>;
>> + d-cache-sets = <64>;
>> + d-cache-size = <32768>;
>> + d-tlb-sets = <1>;
>> + d-tlb-size = <40>;
>> + device_type = "cpu";
>> + i-cache-block-size = <64>;
>> + i-cache-sets = <64>;
>> + i-cache-size = <32768>;
>> + i-tlb-sets = <1>;
>> + i-tlb-size = <40>;
>> + mmu-type = "riscv,sv39";
>> + next-level-cache = <&ccache>;
>> + riscv,isa = "rv64imafdc";
>> + tlb-split;
>> +
>> + cpu4_intc: interrupt-controller {
>> + compatible = "riscv,cpu-intc";
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + };
>> + };
>> +
>> + cpu-map {
>> + cluster0 {
>> + core0 {
>> + cpu = <&S76_0>;
>> + };
>> +
>> + core1 {
>> + cpu = <&U74_1>;
>> + };
>> +
>> + core2 {
>> + cpu = <&U74_2>;
>> + };
>> +
>> + core3 {
>> + cpu = <&U74_3>;
>> + };
>> +
>> + core4 {
>> + cpu = <&U74_4>;
>> + };
>> + };
>> + };
>> + };
>> +
>> + osc: osc {
>
> Node names should be generic, so why this is "osc" and other oscillators
> are not "osc"?
Only "osc" and "rtc_osc" are oscillators, the rest are clock sources provided
through gpio. I will modify the node names according to your link below. So
osc: oscillator {
>
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + rtc_osc: rtc_osc {
>
> No underscores in node names. Generic node names (so each of them
> starting or ending with clock).
Will change this line to
rtc_osc: oscillator {
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac0_rmii_refin: gmac0_rmii_refin {
>
> Same problem... and actually you have way too many fixed clocks which do
Will change the node names as follows.
gmac0_rmii_refin: clock {
...
};
gmac0_rgmii_rxin: clock {
...
};
...
> nothing. It looks like you avoid to define proper clock controller.
> What's the point for all these clocks? These are no-op.
These are all external fixed rate clocks inputted to the SoC. They are the root
clocks of the clock tree made by clock drivers. Their ops are provided in
drivers/clk/clk-fixed-rate.c.
>
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac0_rgmii_rxin: gmac0_rgmii_rxin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac1_rmii_refin: gmac1_rmii_refin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + gmac1_rgmii_rxin: gmac1_rgmii_rxin {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2stx_bclk_ext: i2stx_bclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2stx_lrck_ext: i2stx_lrck_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2srx_bclk_ext: i2srx_bclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + i2srx_lrck_ext: i2srx_lrck_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + tdm_ext: tdm_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + mclk_ext: mclk_ext {
>> + compatible = "fixed-clock";
>> + #clock-cells = <0>;
>> + };
>> +
>> + soc {
>> + compatible = "simple-bus";
>> + interrupt-parent = <&plic>;
>> + #address-cells = <2>;
>> + #size-cells = <2>;
>> + ranges;
>> +
>> + clint: clint@2000000 {
>
> Node names should be generic.
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Change it to
clint: timer@2000000 {
>
>> + compatible = "starfive,jh7110-clint", "sifive,clint0";
>> + reg = <0x0 0x2000000 0x0 0x10000>;
>> + interrupts-extended = <&cpu0_intc 3>, <&cpu0_intc 7>,
>> + <&cpu1_intc 3>, <&cpu1_intc 7>,
>> + <&cpu2_intc 3>, <&cpu2_intc 7>,
>> + <&cpu3_intc 3>, <&cpu3_intc 7>,
>> + <&cpu4_intc 3>, <&cpu4_intc 7>;
>> + };
>> +
>> + plic: plic@c000000 {
>
> Node names should be generic, so interrupt-controller
> https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation
Change it to
plic: interrupt-controller@c000000 {
Best regards,
Hal
>
>> + compatible = "starfive,jh7110-plic", "sifive,plic-1.0.0";
>> + reg = <0x0 0xc000000 0x0 0x4000000>;
>> + interrupts-extended = <&cpu0_intc 11>,
>> + <&cpu1_intc 11>, <&cpu1_intc 9>,
>> + <&cpu2_intc 11>, <&cpu2_intc 9>,
>> + <&cpu3_intc 11>, <&cpu3_intc 9>,
>> + <&cpu4_intc 11>, <&cpu4_intc 9>;
>> + interrupt-controller;
>> + #interrupt-cells = <1>;
>> + #address-cells = <0>;
>> + riscv,ndev = <136>;
>> + };
