On Thu, 2022-10-27 at 10:21 +0200, AngeloGioacchino Del Regno wrote:
> Il 24/10/22 11:42, Garmin.Chang ha scritto:
> > Add MT8188 topckgen clock controller which provides muxes, dividers
> > to handle variety clock selection in other IP blocks.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang@xxxxxxxxxxxx>
> > ---
> > drivers/clk/mediatek/Makefile | 2 +-
> > drivers/clk/mediatek/clk-mt8188-topckgen.c | 1337
> > ++++++++++++++++++++
> > 2 files changed, 1338 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-topckgen.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 957530b4303f..4fc7de25f036 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -82,7 +82,7 @@ obj-$(CONFIG_COMMON_CLK_MT8186) += clk-mt8186-
> > mcu.o clk-mt8186-topckgen.o clk-mt
> > clk-mt8186-mfg.o clk-mt8186-mm.o
> > clk-mt8186-wpe.o \
> > clk-mt8186-img.o clk-mt8186-vdec.o
> > clk-mt8186-venc.o \
> > clk-mt8186-cam.o clk-mt8186-mdp.o
> > clk-mt8186-ipe.o
> > -obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o
> > +obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-apmixedsys.o clk-
> > mt8188-topckgen.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-topckgen.c
> > b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> > new file mode 100644
> > index 000000000000..c6ac6c2558ae
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-topckgen.c
> > @@ -0,0 +1,1337 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang@xxxxxxxxxxxx>
> > +
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +#include "clk-mux.h"
> > +
> > +static DEFINE_SPINLOCK(mt8188_clk_lock);
> > +
> > +static const struct mtk_fixed_clk top_fixed_clks[] = {
> > + FIXED_CLK(CLK_TOP_ULPOSC1, "ulposc_ck1", NULL, 260000000),
> > + FIXED_CLK(CLK_TOP_MPHONE_SLAVE_BCK, "mphone_slave_bck", NULL,
> > 49152000),
> > + FIXED_CLK(CLK_TOP_PAD_FPC, "pad_fpc_ck", NULL, 50000000),
> > + FIXED_CLK(CLK_TOP_466M_FMEM, "hd_466m_fmem_ck", NULL,
> > 533000000),
> > + FIXED_CLK(CLK_TOP_PEXTP_PIPE, "pextp_pipe", NULL, 250000000),
> > + FIXED_CLK(CLK_TOP_DSI_PHY, "dsi_phy", NULL, 500000000),
> > +};
> > +
> > +static const struct mtk_fixed_factor top_divs[] = {
> > + FACTOR(CLK_TOP_MFGPLL, "mfgpll_ck", "mfgpll", 1, 1),
> > + FACTOR(CLK_TOP_MAINPLL, "mainpll_ck", "mainpll", 1, 1),
>
> Are you sure that mainpll and univpll should have
> CLK_SET_RATE_PARENT?
> This will give issues in GPU DVFS, as this is the case with all
> MediaTek SoCs.
>
> Please check this series and add it as a dependency of yours:
>
https://urldefense.com/v3/__https://patchwork.kernel.org/project/linux-mediatek/list/?series=688135__;!!CTRNKA9wMg0ARbw!0ko8NpKA8KW1vp4lw-WRRe2pw_N0Z-2gbeAkzhfmwf9yK25-Bw7TZFfqTTWM_FQFF6A$
>
>
> > + FACTOR(CLK_TOP_MAINPLL_D3, "mainpll_d3", "mainpll_ck", 1, 3),
> > + FACTOR(CLK_TOP_MAINPLL_D4, "mainpll_d4", "mainpll_ck", 1, 4),
>
> ..snip..
>
> > +
> > +static struct mtk_composite top_muxes[] = {
> > + /* CLK_MISC_CFG_3 */
> > + MUX(CLK_TOP_MFG_CK_FAST_REF, "mfg_ck_fast_ref",
> > mfg_fast_ref_parents, 0x0250, 8, 1),
> > +};
>
> CLK_TOP_MFG_CK_FAST_REF is not a composite clock: you can register it
> with a call
> to devm_clk_hw_register_mux() in the probe function.
>
> Check clk-mt8195-topckgen.c upstream for an example.
>
> Regards,
> Angelo
>
Ok, I will use devm_clk_hw_register_mux() in the next version.
> Thanks,
> Best Regards,
> Garmin
